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| m68hc08 microcontrollers freescale.com this document contains information on a new product. specifications and information herein are subject to change without notice . mc68hc08lk60 mc68hc908lk60 advance information data sheet mc68hc08lk60 rev. 1.1 09/2005
mc68hc08lk60 ? mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc., 2005. all rights reserved. mc68hc08lk60 mc68hc908lk60 advance information data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) september, 2005 1.1 updated to meet freescale identity guidelines. throughout revision history mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 4 freescale semiconductor mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 5 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chapter 2 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 chapter 3 random-access memo ry (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 chapter 4 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 chapter 5 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 chapter 6 system integr ation module (sim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 chapter 7 clock generator module (cgmb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 chapter 8 functional cont roller module (fcm ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 chapter 9 break module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 chapter 10 power-on reset module (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 chapter 11 external interrupt module (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 chapter 12 infrared serial communicat ions interface (irsci). . . . . . . . . . . . . . . . . . . . . . 119 chapter 13 serial peripheral interface module (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 chapter 14 alert output generat or (alr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 chapter 15 liquid crystal displ ay module (lcd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 chapter 16 timer interface modul e (tim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 chapter 17 input/output (i/o) port s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 chapter 18 monitor rom (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 chapter 19 keyboard interrupt (k bi) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 chapter 20 preliminary electri cal specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 chapter 21 mechanical da ta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 chapter 22 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 list of chapters mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 6 freescale semiconductor mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.3.1 power supply pins (v dd , v ss , ev dd , and ev ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3.3 external reset pin (rst ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.4 external interrupt pin (irq1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.5 external interrupt pin (irq2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.6 analog ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.7 analog power supply pin (v dda ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.8 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.9 port a i/o pins (pta7?pta0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.10 port b i/o pins (ptb7?ptb0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.11 port c i/o pins (ptc7?ptc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.12 spi master in/slave out (miso) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.13 spi master out/slave in (mosi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.14 spi serial clock (spsck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.15 spi slave select (ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.16 sci receive data (rxd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.17 sci transmit data (txd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.18 alert generator output (alert) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3.19 power supply pins (v ll , v ll32 , v ll12 , and v cp4 ?v cp1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.3.20 frontplane and backplane drivers (fp84?fp0, bp7?bp0). . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 chapter 2 memory map 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.5 monitor read-only memory (rom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 chapter 3 random-access memory (ram) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table of contents mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 8 freescale semiconductor chapter 4 flash memory 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2 flash1 functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3 flash2 functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.4 flash1 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.5 flash2 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.6 flash1 block protect register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.7 flash2 block protect register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.8 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.9 charge pump frequency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.10 flash erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.11 flash program and margin read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 chapter 5 central processor unit (cpu) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 chapter 6 system integrati on module (sim) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.2 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.2.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.2.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.2.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3 reset and system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.2 active resets from internal sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 9 6.3.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.4 sim counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.4.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.4.2 sim counter during stop mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.4.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 6.5 exception control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.5.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.5.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.5.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.5.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.5.4 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.7 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.7.1 sim break status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.7.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.7.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 chapter 7 clock generator module (cgmb) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3.1 crystal oscillator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.3.2 phase-locked loop circuit (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.3.2.1 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.3.2.2 acquisition and tracking modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.3.2.3 manual and automatic pll bandwidth modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.3.2.4 programming the pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.3.2.5 special programming exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.3.3 base clock selector circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.3.4 cgmb external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 7.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.4.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.4.3 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.4.4 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.4.5 pll analog ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.4.6 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.4.7 crystal output frequency signal (cgmxclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.4.8 cgmb base clock output (cgmout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.4.9 cgmb cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table of contents mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 10 freescale semiconductor 7.5 cgmb registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.5.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.5.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 7.5.3 pll multiplier select register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.5.4 pll multiplier select register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 7.5.5 pll vco range select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.5.6 pll reference divider select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.7 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.8 cgmb during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.9 acquisition/lock time specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.9.1 acquisition/lock time definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.9.2 parametric influences on reaction time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.9.3 choosing a filter capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.9.4 reaction time calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 chapter 8 functional controller module (fcm) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.4 module description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.4.1 timebase submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.4.2 real-time clock submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 8.4.3 cop watchdog timer submodule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.6 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.7 interrupt signals (fcm, cpu, and irq). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 8.8 functional controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.8.1 timebase control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.8.2 rtc control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.8.3 rtc status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.8.4 chronograph data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 8.8.5 seconds data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.8.6 minutes data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.8.7 hours data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.8.8 alarm minutes register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.8.9 alarm hours register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 chapter 9 break module 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.3.1 flag protection during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.3.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 08 mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 11 9.3.3 tim during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 08 9.4 break module registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.4.1 break status and control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.4.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 chapter 10 power-on reset module (por) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 10.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 chapter 11 external interrupt module (irq) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.3.1 irq1 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.3.2 irq2 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.4 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.5 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 chapter 12 infrared serial communicat ions interface (irsci) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.3 irsci module overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.4 infrared functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.4.1 infrared transmit encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.4.2 infrared receive decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.5 sci functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.5.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.5.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.5.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 12.5.2.4 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 12.5.2.5 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 12.5.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 12.5.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 12.5.3.2 character reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 12.5.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 12.5.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.5.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.5.3.6 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table of contents mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 12 freescale semiconductor 12.5.3.7 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.5.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.6 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.7 sci during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.8.1 txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.8.2 rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.9 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.9.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.9.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.9.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.9.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.9.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.9.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.9.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.9.8 sci infrared control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 chapter 13 serial peripheral interface module (spi) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.3.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.4 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 13.5 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.5.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1 13.5.2 transmission format when cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.5.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 13.5.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 13.6 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 13.7 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 13.7.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 13.7.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 13.9 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.10 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.11 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.12 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.12.1 master in/slave out (miso). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.12.2 master out/slave in (mosi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.12.3 serial clock (spsck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.12.4 slave select (ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 13.12.5 clock ground (ev ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 13.13 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.13.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.13.2 spi status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 13.13.3 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 13 chapter 14 alert output g enerator (alr) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 14.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 14.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 14.3.1 alert control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.3.2 sound pressure level circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.3.3 alert data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 chapter 15 liquid crystal disp lay module (lcd) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.4 lcd registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.4.1 lcd control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.4.2 lcd address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 15.4.3 lcd data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15.5 anti-ghosting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 15.6 software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15.7 power supply pins (v ll , v ll12 , v ll32 , and v cp1 ?v cp4 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 chapter 16 timer interface module (tim) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.3.1 timer counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.3.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.3.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.3.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.3.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 85 16.3.4 pulse-width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 16.3.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 16.3.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 16.3.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 16.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 16.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 16.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 16.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 16.6 tim during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 16.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 16.7.1 tim clock pin (tclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 16.7.2 timer channel i/o pins (tch0?tch3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table of contents mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 14 freescale semiconductor 16.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 16.8.1 timer status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 0 16.8.2 timer counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 16.8.3 timer modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 16.8.4 timer channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 16.8.5 timer channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 chapter 17 input/output (i/o) ports 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 17.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 17.2.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 17.2.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 17.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.3.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.3.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 17.4 port c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 17.4.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 17.4.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 chapter 18 monitor rom (mon) 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 18.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 18.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 18.3.1 entering monitor mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 18.3.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 18.3.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 18.3.4 break signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 18.3.5 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 chapter 19 keyboard interrupt (kbi) module 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.4 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 19.5 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 19.6 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 19.6.1 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 15 19.6.2 keyboard interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 15 chapter 20 preliminary electri cal specifications 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 20.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 20.3 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 20.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 20.5 3.0 volt 10% dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 20.6 2.0 volt 10% dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 20.7 3.0 volt 10% control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 20.8 2.0 volt 10% control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 20.9 3.0 volt 10% serial peripheral interface (spi) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 20.10 2.0 volt 10% serial peripheral interface (spi) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 20.11 pll2p12m electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 26 20.12 bus clock pll acquisition/lock time s pecifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 20.13 pll2p12m component specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 20.14 ram characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 20.15 flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 chapter 21 mechanical data 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 21.2 160 input/output, bga, standard map, 15 x 15 package (case #1268) . . . . . . . . . . . . . . . . 230 21.3 wire bond information (mcw68hc08lk60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 21.3.1 die pad coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 21.3.2 die layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 21.4 bump wafer information (mccf68hc08lk6 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 21.4.1 bump specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 21.4.2 bumped wafer pad coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 21.4.3 die feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 21.4.4 tape and reel die orientation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 chapter 22 ordering information 22.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 22.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 table of contents mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 16 freescale semiconductor mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 17 chapter 1 general description 1.1 introduction the mc68hc(9)08lk60 is a member of the low-cost, low-power, high-performance m68hc08 family of 8-bit microcontroller units (mcus). the m68hc08 fa mily is based on the customer-specified integrated circuit (csic) design strategy. all mcus in the fa mily use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of mo dules, memory sizes and types, and package types. 1.2 features features of the mc68hc(9)08lk60 include: high-performance m68hc08 architecture fully upward-compatible object code wi th m6805, m146805, and m68hc05 families on-chip rom/flash of 60 kbytes 3.5 kbytes of on-chip mcu ram 24 general-purpose input/output (i/o) pins serial peripheral interface module (spi) infrared serial communications interface module (irsci) with software selectable irda modulation/demodulation clock generation module (cgmb) functional controller module (fcm) with real-time clock lcd module with 85 frontplanes and 8 backplanes alert generator module two external interrupt request (irq) pins 16-bit timer interface module (tim) system protection features: ? computer operating properly (cop) reset in fcm module ? illegal opcode detect with reset ? illegal address detect with reset 160-pin bga package or die low-power design, fully static with wait modes stop mode is disabled master reset pin and power-on reset general description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 18 freescale semiconductor features of the cpu08 include: enhanced hc05 programming model extensive loop control functions 16 addressing modes, 8 more than the hc05 16-bit index register and stack pointer fast 8 x 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications high-level language (c language) support note there is no direct memory access module (dma) in mc68hc(9)08lk60. consequently, the user should disable all the dma functions in all modules. only three ports (ports a, b, and c) are available; ignore all other ports mentioned. no input capture or output compare pins are available for the timer module. 1.3 mcu block diagram figure 1-1 shows the structure of the mc68hc(9)08lk60. mcu block diagram mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 19 figure 1-1. mc68hc(9)08lk60 block diagram ram ? 3.5 kbytes control/status registers ?128 bytes 15 87 0 7 0 15 0 15 0 7 0 vc z n i h a h:x sp pc ccr cpu control arithmetic/ logic unit (alu) pta serial peripheral interface serial communications interface module with irda interface module 16-bit ptaddr pta0 pta1 pta2 pta3 pta4 pta5 pta6 pta7 osc1 data & address bus system clocks functional controller module power ptb ptbddr ptc ptcddr clock generation module monitor rom ? 240 bytes user flash ? 60,928 bytes user flash vector space ? 48 bytes lcd module rst irq1 system integration module osc2 cgmxfc vll vll12 vll32 vcp1,2,3,4 irq2 ptb0 ptb1 ptb2 ptb3 ptb4 ptb5 ptb6 ptb7 ptc0 ptc1 ptc2 ptc3 ptc4 alert alert module bp 0?7 fp 0?84 spsck mosi miso ss rxd txd timer module (tim4) v dd v ssa v dda v ss ev dd ev ss 4 generator 2 2 ptc5 ptc6 ptc7 2 general description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 20 freescale semiconductor 1.3.1 power supply pins (v dd , v ss , ev dd , and ev ss ) the two v dd and two v ss pins are power supply and ground pins for the digital sections of the mcu. the mcu operates from a single-power supply ranging from 2 volts ( 10%) to 3 volts ( 10%). the ev dd and ev ss pins are power supply and ground pins for the i/o section of the mcu. very fast signal transitions on the mcu pins plac e high, short-duration current demands on the power supply. to prevent noise problems, take special care to provide good power supply bypassing at the mcu as shown in figure 1-2 . place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response ceramic capacitor for c1. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. ev ss pin is also the ground return pin for the serial cl ock in the serial peripheral interface module (spi). it enables the user to implement a coplanar transmission line for the sp i clock on printed circuit boards (pcbs) with no ground plane. ev ss can help reduce radiated radi o frequency (rf) emissions by controlling trace impedance and mi nimizing radiating loop area. see chapter 13 serial peripheral interface module (spi) for more information. figure 1-2. power supply bypassing note component values shown repres ent typical applications. 1.3.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins are the crystal connections for the on-chip oscillator. figure 1-3 shows a typical crystal oscillator circuit for a parallel resonant crysta l. follow the crystal supplier?s recommendations, as the crystal parameters determine the external compone nt values required to provide reliable startup and maximum stability. the load capacitanc e values used in the oscillator circuit design should include all stray layout capacitances. to minimize output dist ortion and radio frequency (rf) emissions, mount the crystal and capacitors as close as possible to the pins . pay special attention to minimizing the length of the oscillator load capacitors? ground return path. mcu v dd c2 c1 0.1 f v ss v dd + mcu block diagram mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 21 figure 1-3. crystal connections note component values shown represent typi cal applications. follow the crystal manufacturer?s recommendations. 1.3.3 external reset pin (rst ) a logic 0 on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. see chapter 6 system integration module (sim) for more information. 1.3.4 external in terrupt pin (irq1 ) irq1 is an asynchronous external interrupt pin. see chapter 6 system integration module (sim) and chapter 11 external interrupt module (irq) for more information. 1.3.5 external in terrupt pin (irq2 ) irq2 is an asynchronous external interrupt pin. see see chapter 6 system integration module (sim) and chapter 11 external interrupt module (irq) for more information. 1.3.6 analog ground pin (v ssa ) the v ssa analog ground pin is used only for the ground c onnections for the analog sections of the clock generator module (cgm) and should be decoupled as per the v ss digital ground pin. see 7.1 introduction for more information. 1.3.7 analog power supply pin (v dda ) v dda is the power supply pin for the analog portion of the clock generator module (cgm). see 7.1 introduction for more information. 1.3.8 external filter capacitor pin (cgmxfc) cgmxfc is an external filter c apacitor connection for the cgm. see 7.1 introduction for more information. osc1 osc2 xtal 22 m ? mcu 27 pf 27 pf 38.4 khz 330 k ? general description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 22 freescale semiconductor 1.3.9 port a i/o pins (pta7 ? pta0) pta7?pta0 are general-purpose bidirectional i/o port pins. see chapter 17 input/output (i/o) ports for more information. 1.3.10 port b i /o pins (ptb7?ptb0) ptb7?pbc0 are general-purpose bidirectional i/o port pins. see chapter 17 input/output (i/o) ports for more information. 1.3.11 port c i /o pins (ptc7?ptc0) ptc7?ptc0 are general-purpose bidirectional i/o port pins. see chapter 17 input/output (i/o) ports for more information. 1.3.12 spi master in/slave out (miso) miso is used in the spi to receive/transmit data in the spi module. see chapter 13 serial peripheral interface module (spi) for more information. 1.3.13 spi master out/slave in (mosi) mosi is used in the spi to receive/transmit data in the spi module. see chapter 13 serial peripheral interface module (spi) for more information. 1.3.14 spi seri al clock (spsck) spsck is the serial clock of the spi that synchronizes data transmi ssion between master and slave devices. see chapter 13 serial peripheral interface module (spi) for more information. 1.3.15 spi sl ave select (ss ) ss is the slave select of the spi that indicate that the slave is enabled to receive data when the pin is at logic 0. see chapter 13 serial peripheral interface module (spi) for more information. 1.3.16 sci r eceive data (rxd) the rxd pin is serial data input to the sci receiver. see chapter 12 infrared serial communications interface (irsci) for more information. 1.3.17 sci tran smit data (txd) the txd pin is the serial data out put from the sci transmitter. see chapter 12 infrared serial communications interface (irsci) for more information. 1.3.18 alert genera tor output (alert) this is the output from the alert generator module. see chapter 14 alert output generator (alr) for more information. pin assignments mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 23 1.3.19 power supply pins (v ll , v ll32 , v ll12 , and v cp4 ?v cp1 ) these are power supply pins for the lcd (liquid crystal display) voltage converter. these pins should be connected in a certain configuration in order for the charge pump to work correctly. see chapter 15 liquid crystal display module (lcd) for detailed hookup configuration. 1.3.20 frontplane and backplane drivers (fp84?fp0, bp7?bp0) these are frontplane (fp84?fp0) and backplane ( bp7?bp0) drivers for an lcd display. see chapter 15 liquid crystal display module (lcd) for more information. 1.4 pin assignments the mc68hc(9)08lk60 is available in a 160-pin bg a package. the pin assignments for this package are shown in figure 1-4 . general description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 24 freescale semiconductor figure 1-4. 160-pin bga pin assignments ev ss v ss bp7 bp4 fp83 fp80 fp77 fp73 fp71 fp67 fp65 fp62 fp59 fp56 ptc0 alert fp84 fp81 fp79 fp75 fp72 fp69 fp66 fp63 fp61 fp57 fp54 ptc3 ptc2 ev dd bp6 v dd fp78 fp74 fp70 fp60 fp58 fp55 fp52 fp51 ptc5 ptc4 ptc1 ptc7 bp5 fp82 fp76 fp68 fp64 fp53 fp50 fp48 ptb0 ptb2 ev ss ptb1 fp46 fp44 fp47 fp45 ptb4 ptb5 ptb6 ptb3 v cp4 fp49 fp43 v ll32 ptb6 pta2 ptb7 pta0 v cp2 v cp3 v cp1 v ll12 pta3 pta4 pta1 pta5 fp41 fp42 v ll pta6 irq2 miso irq1 fp39 fp31 fp38 fp40 ev ss sck pta7 fp33 fp35 fp36 mosi ss osc2 bp0 fp0 fp8 fp14 fp18 fp22 fp37 fp32 fp34 tdo rdi v dda osc1 fp2 fp6 fp12 fp16 fp24 fp25 fp29 fp30 rst ev dd v ssa v ss bp2 fp1 fp4 fp7 fp10 fp13 fp19 fp21 fp27 fp28 ev ss v dd bp1 bp3 fp3 fp5 fp9 fp11 fp15 fp17 fp20 fp23 fp26 cgm- xfc a b c d e f g h j k l m n p 1234567891011121314 mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 25 chapter 2 memory map 2.1 introduction the central processor unit (cpu08) can address 64 kb ytes of memory space. the memory map, shown in figure 2-1 , includes: 60 kbytes of flash 3.5 kbytes of ram 48 bytes of user-defined vectors 240 bytes of monitor rom 2.2 i/o section addresses $0000?$003f, shown in figure 2-2 , contain most of the control, status, and data registers. additional input/output (i/o) registers ( figure 2-3 ) have these addresses: $fe00, sim break status register (sbsr) $fe01, sim reset status register (srsr) $fe03, sim break flag control register (sbfcr) $fe09, flash2 control register (fl2cr) $fe08, flash1 control register (fl1cr) $fe0c and $fe0d, break address registers (brkh and brkl) $fe0e, break status and control register (brkscr) 2.3 random-access memory (ram) the 3584 addresses from $0040?$0e3f are ram loca tions. the location of the stack ram is programmable. the 16-bit stack pointer allows the st ack to be anywhere in ram, allowing all page zero locations to be used for i/o control and user data or c ode. within page zero there are 192 bytes of ram. when the stack pointer is moved from its reset location at $00ff, direct addressing mode instructions can access all page zero ram locations efficiently. page ze ro ram, therefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note to maintain m6805 compatibility, the upper byte of the index register (h) is not stacked automatically. if the interru pt service routine modifies h, then the user must stack and unstack h us ing the pshh and pulh instructions. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. memory map mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 26 freescale semiconductor note be careful when using nested subroutines or multiple interrupt levels. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking. 2.4 memory map see figure 2-1 , figure 2-2 , figure 2-3 , and figure 2-4 . $0000 i/o registers ? 64 bytes $003f user ram ? 192 bytes stack ? 64 bytes $00ff $0100 page 1 user ram ? 3392 bytes $0e3f $0e40 unused ? 448 bytes $0fff $1000 user flash ? 60,928 bytes (~ 60 k) $fdff $fe00 sim registers ? 16 bytes $fe10 monitor rom ? 240 bytes $feff $ff00 unused ? 208 bytes $ffcf $ffd0 user vectors ? 48 bytes $ffff figure 2-1. memory map memory map mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 27 addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: ptc7 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset: 0 0 0 0 0 0 0 0 $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0 0 0 0 0 0 0 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 0 0 0 0 0 0 0 0 $0006 data direction register c (ddrc) read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 0 0 0 0 0 0 0 0 $0007 pll control register (pctl) read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset: 0 0 1 0 1 1 1 1 $0008 pll bandwidth control register (pbwc) read: auto lock acq 0000 r write: reset: 0 0 0 0 0 0 0 0 $0009 pll multiplier select register high (pmsh) read: 0 0 0 0 mul11 mul10 mul9 mul8 write: reset: 0 0 0 0 0 0 0 0 $000a pll multiplier select register low (pmsl) read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset: 0 1 0 0 0 0 0 0 $000b pll vco range select register (pvrs) read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset: 0 1 0 0 0 0 0 0 = unimplemented u = undetermined x = indeterminate figure 2-2. control, status, and data registers (sheet 1 of 5) memory map mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 28 freescale semiconductor $000c pll reference divider select register (prds) read: 0 0 0 0 rds3 rds2 rds1 rds0 write: reset: 0 0 0 0 0 0 0 1 $000d spi control register (spcr) read: sprie dmas spmstr cpol cpha spwom spe sptie write: reset: 0 0 1 0 1 0 0 0 $000e spi status and control register (spscr) read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset: 0 0 0 0 1 0 0 0 $000f spi data register (spdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset $0010 unimplemented $0011 alert control register (alcr) read: 0 0 0 0 al3 al2 al1 al0 write: reset: 0 0 0 0 0 0 0 0 $0012 alert data register (aldr) read: spl7 spl6 spl5 spl4 spl3 spl2 spl1 spl0 write: reset: 0 0 0 0 0 0 0 0 $0013 sci control register 1 (scc1) read: loops ensci 0 m wake ilty pen pty write: reset: 0 0 0 0 0 0 0 0 $0014 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $0015 sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset: u u 0 0 0 0 0 0 $0016 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset: 1 1 0 0 0 0 0 0 $0017 sci status register 2 (scs2) read: bkf rpf write: reset: 0 0 0 0 0 0 0 0 $0018 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented u = undetermined x = indeterminate figure 2-2. control, status, and data registers (sheet 2 of 5) memory map mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 29 $0019 sci baud rate register (scbr) read: 0 0 0 0 0 scr2 scr1 scr0 write: reset: 0 0 0 0 0 0 0 0 $001a lcd control register (lcdcr) read: duty1 duty0 agon dsmin motmd 0 0 0 write: reset: 0 0 0 0 0 0 0 0 $001b lcd address register (lcdar) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $001c lcd data register (lcddr) read: bp7 bp6 bp5 bp4 bp3 bp2 bp1 bp0 write: reset: 0 0 0 0 0 0 0 0 $001d irq status and control register (iscr) read: pin2 0 imask2 mode2 irq2dis 0 imask1 mode1 write: ack2 ack1 reset: 0 0 0 0 0 0 0 0 $001e sci infrared control register (scircr) read: 0 0 0 0 0 tnp1 tnp0 iren write: reset: 0 0 0 0 0 0 0 0 $001f unimplemented $0020 tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 0 0 0 0 0 0 0 0 $0021 unimplemented $0022 tim counter register high (tcnth) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0023 tim counter register low (tcntl) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0024 tim counter modulo register high (tmodh) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0025 tim counter modulo register low (tmodl) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented u = undetermined x = indeterminate figure 2-2. control, status, and data registers (sheet 3 of 5) memory map mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 30 freescale semiconductor $0026 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0027 tim channel 0 register high (tch0h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0028 tim channel 0 register low (tch0l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0029 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 0 0 0 0 0 0 0 0 $002a tim channel 1 register high (tch1h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002b tim channel 1 register low (tch1l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $002c tim channel 2 status and control register (tsc2) read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 0 0 0 0 0 0 0 0 $002d tim channel 2 register high (tch2h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002e tim channel 2 register low (tch2l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $002f tim channel 3 status and control register (tsc3) read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset: 0 0 0 0 0 0 0 0 $0030 tim channel 3 register high (tch3h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0031 tim channel 3 register low (tch3l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0032 flash2 block protect register (fl2bpr) read: write: bpr3 bpr2 bpr1 bpr0 reset: x x x x 1 1 1 1 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented u = undetermined x = indeterminate figure 2-2. control, status, and data registers (sheet 4 of 5) memory map mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 31 $0033 flash1 block protect register (fl1bpr) read: write: bpr3 bpr2 bpr1 bpr0 reset: x x x x 1 1 1 1 $0034 unimplemented $0035 timebase control register (tbcr) read: rtce 0 chrc crs1 crs0 r tb2x tb0 write: tbclr reset: 0 0 0 0 0 0 0 0 $0036 rtc control register (rtccr read: hrie minie secie chrie chrce alien prq1 prq0 write: reset: 0 0 0 0 0 0 0 0 $0037 rtc status register (rtcsr) read: 0 0 prqf horf minf secf aflg chrf write: reset: 0 0 0 0 0 0 0 0 $0038 chronograph data register (chrdr) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0039 rtc seconds register (secr) read: 0 0 sec5 sec4 sec3 sec2 sec1 sec0 write: reset: 0 0 0 0 0 0 0 0 $003a rtc minutes register (minr) read: 0 0 min5 min4 min3 min2 min1 min0 write: reset: 0 0 0 0 0 0 0 0 $003b rtc hours register (horr) read: 0 0 0 hor4 hor3 hor2 hor1 hor0 write: reset: 0 0 0 0 0 0 0 0 $003c alarm minutes register (alrmr) read: 0 0 am5 am4 am3 am2 am1 am0 write: reset: 0 0 0 0 0 0 0 0 $003d alarm hours register (alrhr) read: 0 0 0 ah4 ah3 ah2 ah1 ah0 write: reset: 0 0 0 0 0 0 0 0 $003e unimplemented $003f unimplemented addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented u = undetermined x = indeterminate figure 2-2. control, status, and data registers (sheet 5 of 5) memory map mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 32 freescale semiconductor addr. register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note 1 reset: 0 note 1. writing a logic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 lvi 0 write: reset:10000000 $fe02 reserved $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 reserved $fe05 reserved $fe06 reserved $fe07 reserved $fe08 reserved $fe09 flash2 control register (fl2cr) read: fdiv1 fdiv0 blk1 blk0 hven marg erase pgm write: reset:00000000 $fe0a reserved $fe0b flash1 control register (fl1cr) read: fdiv1 fdiv0 blk1 blk0 hven marg erase pgm write: reset:00000000 $fe0c break address register high (brkh) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $fe0e break status/control register (brkscr) read: brke brka 000000 write: reset:00000000 $fe0f unimplemented r =reserved = unimplemented figure 2-3. sim registers memory map mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 33 $ffd0 reserved $ffd1 reserved $ffd2 external irq2/kbi vector (high) $ffd3 external irq2/kbi vector (low) $ffd4 sci module transmit vector (high) $ffd5 sci module transmit vector (low) $ffd6 sci module receive vector (high) $ffd7 sci module receive vector (low) $ffd8 sci module error vector (high) $ffd9 sci module error vector (low) $ffda reserved $ffdb reserved $ffdc reserved $ffdd reserved $ffde spi 1 module transmit vector (high) $ffdf spi 1 module transmit vector (low) $ffe0 spi 1 module receive vector (high) $ffe1 spi 1 module receive vector (low) $ffe2 reserved $ffe3 reserved $ffe4 reserved $ffe5 reserved $ffe6 fcm module vector (high) $ffe7 fcm module vector (low) $ffe8 reserved $ffe9 reserved $ffea tim overflow vector (high) $ffeb tim overflow vector (low) $ffec tim channel 3 vector (high) $ffed tim channel 3 vector (low) $ffee tim channel 2 vector (high) $ffef tim channel 2 vector (low) $fff0 tim channel 1 vector (high) $fff1 tim channel 1 vector (low) $fff2 tim channel 0 vector (high) figure 2-4. vector addresses in flash/rom (sheet 1 of 2) memory map mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 34 freescale semiconductor 2.5 monitor read-only memory (rom) the 240 bytes at addresses $fe10?$feff are reserved rom addresses that contain instructions for the monitor functions. for more information, see chapter 18 monitor rom (mon) . $fff3 tim channel 0 vector (low) $fff4 reserved $fff5 reserved $fff6 reserved $fff7 reserved $fff8 pll module vector (high) $fff9 pll module vector (low) $fffa irq1 vector (high) $fffb irq1 vector (low) $fffc swi vector (high) $fffd swi vector (low) $fffe reset vector (high) $ffff reset vector (low) figure 2-4. vector addresses in flash/rom (sheet 2 of 2) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 35 chapter 3 random-access memory (ram) 3.1 introduction this section describes the 3584 bytes of random-access memory (ram). 3.2 functional description addresses $0040?$0e3f are ram locations. the locati on of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. note for correct operation, the stack pointer must point only to ram locations. within page zero are 192 bytes of ram. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o (input/output) control and user data or code. when the stack pointer is moved from its reset location at $00ff, direct addressing mode instructions can access all page zero ram locations efficiently. page zero ram, therefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note for m6805 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note be careful when using nested subrouti nes. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. random-access memory (ram) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 36 freescale semiconductor mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 37 chapter 4 flash memory 4.1 introduction this section describes the operation of the em bedded 60-kbyte flash memory. the flash memory consists of two modules: flash1 ? ~32 kbytes, address range is $8000?$fdff and $ffd0?$ffff flash2 ? 28 kbytes, address range $1000?$7fff flash memory is non-volatile and can be read, programmed, and erased from a single external supply. 4.2 flash1 functional description the flash1 memory array contains 32,304 bytes. an erased bit reads as a logic 0 and a programmed bit reads as a logic 1. program and erase operations are facilitated through control bits in a memory mapped register. for a dditional details, see 4.10 flash erase operation and 4.11 flash program and margin read operation . memory in the flash array is organized into pages and rows. there are eight pages of memory per row, and for this array, there are eight bytes per page. t he minimum erase block size is a single row, 64 bytes. programming is performed on a per-page basis, or for this array, eight bytes at a time. these are the address ranges for the 32-kbyte flash memory: $8000?$fdff, user flash array $ffd0?$ffff, user vector space addr. register name bit 7 6 5 4 3 2 1 bit 0 $0032 flash2 block protect register (fl2bpr) read: write: bpr3 bpr2 bpr1 bpr0 reset: x x x x 1 1 1 1 $0033 flash1 block protect register (fl1bpr) read: write: bpr3 bpr2 bpr1 bpr0 reset: x x x x 1 1 1 1 $fe09 flash2 control register (fl2cr) read: fdiv1 fdiv0 blk1 blk0 hven marg erase pgm write: reset: 0 0 0 0 0 0 0 0 $fe0b flash1 control register (fl1cr) read: fdiv1 fdiv0 blk1 blk0 hven marg erase pgm write: reset: 0 0 0 0 0 0 0 0 = unimplemented x = indeterminate figure 4-1. flash register summary flash memory mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 38 freescale semiconductor when programming the flash, just enough program time must be utilized via an iterative programming algorithm. too much program time can result in a disturb condition in which an erased bit becomes programmed. this can be prevented as long as no more than eight program operations are performed per row before again performing an erase operation. each programmed page is read in margin mode to ensure that the bits are programmed enough for data retention over the device?s lifetime. the row architecture for this array is: 4.3 flash2 functional description the flash2 memory array contains 28,672 bytes. an erased bit reads as a logic 0 and a programmed bit reads as a logic 1. program and erase operations are facilitated through control bits in a memory mapped register. details for these operations appear later in this section. memory in the flash array is organized into pages and rows. there are eight pages of memory per row, and for this array, there are eight bytes per page. t he minimum erase block size is a single row, 64 bytes. programming is performed on a per page basis, or for this array, eight bytes at a time. address range for the 28-kbyte flash memory is $1000?$7fff. when programming the flash, just enough program time must be utilized via an iterative programming algorithm. too much program time can result in a disturb condition in which an erased bit becomes programmed. this can be prevented as long as no more than eight program operations are performed per row before again performing an erase operation. each programmed page is read in margin mode to ensure that the bits are programmed enough for data retention over the device?s lifetime. 4.4 flash1 control register the flash1 control register (fl1cr) controls flash program, erase, and margin operations. caution devices with more than one flash have multiple control registers (flcrs.) only one flash control register should be accessed at a time. so, while accessing one control register, ensure that any others are cleared. $8000?$803f row 0 $8040?$807f row 1 $8080?$80bf row 2 $ffd0?$ffff row 504 address: $fe0b bit 7654321bit 0 read: fdiv1 fdiv0 blk1 blk0 hven marg erase pgm write: reset:00000000 figure 4-2. flash1 control register (fl1cr) flash1 control register mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 39 fdiv0 ? frequency divide control bit this bit selects the factor by which cgmvclk is divided to derive the charge pump frequency. see table 4-3 . note fdiv1 has no effect. blk1 and blk0 ? block erase control bits these bits control erasing of blocks of varying size. table 4-1 shows the various block sizes which can be erased in one erase operation. in step 4 of the erase operation (see 4.10 flash erase operation ), the upper addresses are latched and used to determine the location of the block to be erased. for the full array, the only requirement is that the target address points to any byte in this array. writing to any address in the array will enable the erase. hven ? high voltage enable bit this read/write bit enables high voltage from the c harge pump to the memory for either program or erase operation. it can only be set if either pgm or erase is set. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off marg ? program margin control bit this read/write bit configures the memory for a prog ram margin operation. it cannot be set if the hven bit is set, and if it is set when hven is set, it will automatically return to 0. 1 = margin operation selected 0 = margin operation unselected erase ? erase control bit this read/write bit configures the memory for erase operation. it is interlocked with the pgm bit such that both bits cannot be set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures t he memory for program operation. it is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected table 4-1. erase block sizes of flash1 blk1 blk0 block size row boundaries 0 0 full array: 32 kbytes 0-504 ($8000?$ffff) 0 1 one-half array: 16 kbytes 0-255 ($8000?$bfff) 256-504 ($c000?$ffff) 1 0 eight rows: 512 bytes 0?7 ($8000?$81ff) 8?15 ($8200?$83ff) 16?23 ($8400?$85ff) 496?503 ($fc00?$fdff) 1 1 single row: 64 bytes 0 ($8000?$803f) 1 ($8040?$807f) 504 ($ffd0?$ffff) flash memory mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 40 freescale semiconductor 4.5 flash2 control register the flash2 control register controls flash program, erase, and margin operations. fdiv0 ? frequency divide control bit this bit selects the factor by which cgmvclk is divided to derive the charge pump frequency. see table 4-3 . note fdiv1 has no effect. blk1 and blk0 ? block erase control bits these bits control erasing of blocks of varying size. table 4-2 shows the various block sizes which can be erased in one erase operation. in step 4 of the erase operation (see 4.10 flash erase operation ), the upper addresses are latched and used to determine the location of the block to be erased. for the full array, the only requirement is that the target address points to any byte in this array. writing to any address in the array will enable the erase. hven ? high-voltage enable bit this read/write bit enables high voltage from the c harge pump to the memory for either program or erase operation. it can only be set if either pgm or erase is set. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off marg ? program margin control bit this read/write bit configures the memory for a prog ram margin operation. it cannot be set if the hven bit is set, and if it is set when hven is set, it will automatically return to 0. 1 = margin operation selected 0 = margin operation unselected erase ? erase control bit this read/write bit configures the memory for erase operation. it is interlocked with the pgm bit such that both bits cannot be set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected address: $fe09 bit 7654321bit 0 read: fdiv1 fdiv0 blk1 blk0 hven marg erase pgm write: reset:00000000 figure 4-3. flash2 control register (fl2cr) table 4-2. erase block sizes of flash2 blk1 blk0 block size row boundaries 0 0 full array: 28 kbytes $1000?$7fff 0 1 one-half array 12 kbytes; $1000?$3fff 16 kbytes; $4000?$7fff 1 0 eight rows: 512 bytes ? 1 1 single row: 64 bytes ? flash1 block protect register mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 41 pgm ? program control bit this read/write bit configures t he memory for program operation. it is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected 4.6 flash1 block protect register the block protect register is implemented as an i nput/output (i/o) register. each bit, when programmed, protects a range of addresses in the flash. bpr3 ? block protect register bit 3 this bit protects the memory contents in the address range $c000?$ffff. 1 = address range protected from erase or program 0 = address range open to erase or program bpr2 ? block protect register bit 2 this bit protects the memory contents in the address range $a000?$ffff. 1 = address range protected from erase or program 0 = address range open to erase or program bpr1 ? block protect register bit 1 this bit protects the memory contents in the address range $9000?$ffff. 1 = address range protected from erase or program 0 = address range open to erase or program bpr0 ? block protect register bit 0 this bit protects the memory contents in the address range $8000?$ffff. 1 = address range protected from erase or program 0 = address range open to erase or program by programming the block protect bits, a portion of the memory will be locked so that no further erase or program operations may be performed. programming more than one bit at a time is redundant. for instance, if both bpr3 and bpr2 are set, the address range $a000?$ffff is locked. if all bits are cleared, then all of the memory is available for erase and program. address: $0033 bit 7654321bit 0 read: write: bpr3 bpr2 bpr1 bpr0 reset:xxxx 1111 = unimplemented x = indeterminate figure 4-4. flash1 block protect register (fl1bpr) flash memory mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 42 freescale semiconductor 4.7 flash2 block protect register the block protect register is implemented as an i/ o register. each bit, when programmed, protects a range of addresses in the flash. bpr3 ? block protect register bit 3 this bit protects the upper half portion of full-s ize 32-k array. since flash2 is 28 kbytes, the block protect address range is $4000?$7fff. 1 = address range protected from erase or program 0 = address range open to erase or program bpr2 ? block protect register bit 2 this bit protects the upper 3/4 portion of full-siz e 32-k array. since flash2 is 28 kbytes, the block protect address range is $2000?$7fff. 1 = address range protected from erase or program 0 = address range open to erase or program bpr1 ? block protect register bit 1 this bit protects the upper 7/8 portion of a full si ze 32-k array. since flash2 is 28 kbytes, the block protect address range is $1000?$7fff. 1 = address range protected from erase or program 0 = address range open to erase or program bpr0 ? block protect register bit 0 this bit protects all the memory contents in the address range $1000?$7fff. 1 = address range protected from erase or program 0 = address range open to erase or program by programming the block protect bits, a portion of the memory will be locked so that no further erase or program operations may be performed. programming more than one bit at a time is redundant. if both bpr3 and bpr2 are set, for instance, the address ran ge $2000?$7fff is locked. if all bits are cleared, then all of the memory is available for erase and program. 4.8 block protection because of the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made for protecting bl ocks of memory from unintentional erase or program operations. this protection is done by reserving a lo cation in the i/o space for block protect information. if the address range for an erase or program operati on includes a protected block, the pgm or erase bit is cleared which prevents the hven bit in the fl ash control register from being set so that no high voltage is allowed in the array. address: $0032 bit 7654321bit 0 read: write: bpr3 bpr2 bpr1 bpr0 reset:xxxx 1111 = unimplemented x = indeterminate figure 4-5. flash2 block protect register (fl2bpr) charge pump frequency control mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 43 when the block protect register is cleared, the entir e memory is accessible for program and erase. when bits within the register are programmed, they lock blocks of memory address ranges as shown in 4.6 flash1 block protect register and 4.7 flash2 block protect register . 4.9 charge pump frequency control the internal charge pump for this array is to be operated over the specified frequency range (refer to table 4-3 ). the pll output clock, cgmvclk, is us ed to derive the two quadrature clocks, vclk12 and vclk23, which are one-half cgmvclk. additional pum p frequency control is provided using the fdiv0 bit in order to keep the vclks within the spec ified range. the pll must be on and locked (but not necessarily engaged) before program/erase operations can be performed. 4.10 flash erase operation note after a total of eight program operati ons has been applied to a row, the row must be erased before further use in or der to avoid a disturb condition. an erased byte will read $00. in 20.15 flash memory electrical characteristics , a detailed description of the times used in this algorithm is given. use this procedure to erase a block of flash memory: 1. establish pump frequency by configuring pll. 2. unprotect target portion of the array, bpr0?bpr3. 3. set the erase bit, the blk0, blk1, and fdiv0 bits in the flash control register. 4. write to any flash address with any data within the block address range desired. 5. set the hven bit. 6. wait for a time, t e rase . 7. clear the hven bit. 8. wait for a time, t k ill , for the high voltages to dissipate. 9. clear the erase bit. 10. after a time, t hvd , the memory can be accessed in read mode again. caution these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. do not exceed t erase maximum. table 4-3. charge pump clock frequency fdiv0 pump clock frequency 0 cgmvclk 2 1 cgmvclk 4 flash memory mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 44 freescale semiconductor 4.11 flash program and margin read operation programming of this flash array is done on a page basis where one page equals eight bytes. the purpose of the margin read mode is to ensure that data has been programmed with sufficient margin for long term data retention. during a margin read, the cont rol gates of the selected memory bits are held at a slightly negative voltage by an in ternal charge pump. reading the data in margin mode is the same as for ordinary read mode except that a built-in counter stretches the data access for an additional eight cycles to allow sensing of the lower cell current. in short, a margin read applies a more stringent condition on the bitcell during read which ensur es the data will be valid throughout the life of the product. a margin read can only follow a program operation. refer to chapter 20 preliminary electrical specifications . the procedure for programming the flash memory is: 1. establish pump frequency by configuring the pll. 2. set the pgm bit and program fdiv0 appropriately. this configures the memory for program operation and enables the latching of address and data for programming. 3. write data to the page (eight bytes) being programmed. 4. set the hven bit. 5. wait for a time, t step . 6. clear the hven bit. 7. wait for a time, t hvtv . 8. set the marg bit. 9. wait for a time, t vtp . 10. clear the pgm bit. 11. wait for a time, t hvd . 12. read the page of data (this is in margin mode.) 13. clear the marg bit. 14. if any programmed bits do not read correctly, repe at the process from step 2 through step 13 up to maximum program pulses (see chapter 20 preliminary el ectrical specifications ). flash program and marg in read operation mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 45 figure 4-6. page program algorithm program 60-k flash initialize attempt set pgm bit and fdiv bits wait t hvtv wait t vtp set hven bit clear pgm bit set margin bit wait t hvd increment attempt y counter to 0 y n programming operation failed programming operation complete write data to selected page wait t step clear hven bit read page of data clear margin bit read data equal to write data? attempt count equal to 5? note: this page program algorithm assumes the pll is on and locked and the page to be programmed has been erased before entry. counter n flash memory mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 46 freescale semiconductor mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 47 chapter 5 central processor unit (cpu) 5.1 introduction the m68hc08 cpu (central processor unit) is an e nhanced and fully object-code- compatible version of the m68hc05 cpu. the cpu08 reference manual (document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 5.2 features features of the cpu include: object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-re gister manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes low-power stop and wait modes 5.3 cpu registers figure 5-1 shows the five cpu registers. cpu registers are not part of the memory map. central processor unit (cpu) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 48 freescale semiconductor figure 5-1. cpu registers 5.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. 5.3.2 index register the 16-bit index register allows i ndexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, th e cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. bit 7654321bit 0 read: write: reset: unaffected by reset figure 5-2. accumulator (a) bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 5-3. index register (h:x) accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 cpu registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 49 5.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset a ddressing modes, the stack pointer can function as an index register to access data on t he stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 5.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increm ents to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 5-4. stack pointer (sp) bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 5-5. program counter (pc) central processor unit (cpu) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 50 freescale semiconductor 5.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set per manently to 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. th e daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cp u interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note to maintain m6805 family compatibil ity, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priori ty interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 5-6. condition code register (ccr) arithmetic/logic unit (alu) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 51 z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 5.4 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 5.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 5.5.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. disables the cpu clock 5.5.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 5.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. central processor unit (cpu) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 52 freescale semiconductor a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. 5.7 instruction set summary table 5-1 provides a summary of the m68hc08 instruction set. table 5-1. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 c b0 b7 0 b0 b7 c instruction set summary mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 53 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 table 5-1. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 54 freescale semiconductor cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 5-1. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc instruction set summary mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 55 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 table 5-1. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 central processor unit (cpu) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 56 freescale semiconductor ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ? dir 35 dd 4 stop enable interrupts, stop processing, refer to mcu documentation i 0; stop processing ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 table 5-1. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c opcode map mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 57 5.8 opcode map see table 5-2 . sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 wait enable interrupts; wait for interrupt i bit 0; inhibit cpu clocking until interrupted ??0???inh 8f 1 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit ? not affected table 5-1. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 58 freescale semiconductor central processor unit (cpu) table 5-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 59 chapter 6 system integration module (sim) 6.1 introduction this section describes the system integration module (sim24, version c), which supports up to 24 external and/or internal interrupts. together with the cpu, the sim controls all mcu activities. a block diagram of the sim is shown in figure 6-1 . figure 6-2 is a summary of the sim i/o (input/output) registers. the sim is a system state controller that coordinat es cpu and exception timing. the sim is responsible for: bus clock generation and control for cpu and peripherals: ? stop/wait/reset/break entry and recovery ? internal clock control master reset control, including power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture expandable to 128 interrupt sources note all references to lvi and dma and stop mode operation in this section should be ignored. table 6-1 shows the internal signal names used in this section. table 6-1. signal name conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmvclk pll output cgmout pll-based or osc1-based cl ock output from cgm module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal system integration module (sim) mc68hc08lk60 ? mc68hc908lk60 advance information data sheet, rev. 1.1 60 freescale semiconductor figure 6-1. sim block diagram addr. register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note 1 reset: 0 $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 lvi 0 write: reset:10000000 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 note 1. writing a logic 0 clears sbsw. r =reserved = unimplemented figure 6-2. sim i/o register summary stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop; from cpu cpu wait; from cpu simoscen; to cgm cgmout; from cgm internal clocks master reset control reset pin logic lvi; from lvi module illegal opcode; from cpu illegal address; from address map decoders cop; from cop module interrupt sources cpu interface reset control sim counter cop clock cgmxclk; from cgm 2 sim bus clock control and generation mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 61 6.2 sim bus clock control and generation the bus clock generator provides system clock signa ls for the cpu and peripherals on the mcu. the system clocks are generated from an in coming clock, cgmout, as shown in figure 6-3 . this clock can come from either an external oscillat or or from the on-chip pll. (see 7.1 introduction .) 6.2.1 bus timing in user mode , the internal bus frequency is either the crys tal oscillator output (cgmxclk) divided by four or the pll output (cgmvclk) divided by four. (see 7.1 introduction .) 6.2.2 clock startup from por or lvi reset when the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inac tive phase until after the 4096 cgmxclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the ibus clocks start upon completion of the timeout. note the mc68hc(9)08lk60 does not have an lvi module. figure 6-3. cgm clock signals 6.2.3 clocks in st op mode and wait mode upon exit from stop mode (by an interrupt, break, or reset), the sim allows cgmxclk to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 32 cgmxclk cycles. (see 6.6.2 stop mode .) note the mc68hc(9)08lk60 does not allow stop mode operation. in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to s ee if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. pll osc1 cgmxclk 2 bus clock generators sim cgm sim counter ptc3 monitor mode clock select circuit cgmvclk bcs 2 a b s* cgmout *when s = 1, cgmout = b user mode system integration module (sim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 62 freescale semiconductor 6.3 reset and system initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) low-voltage inhibit module (lvi) illegal opcode illegal address all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all register s to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 6.4 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). (see 6.7 sim registers .) 6.3.1 external pin reset pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 cgmxclk cycles, assuming that neither the por nor the lvi was the source of the reset. see table 6-2 for details. figure 6-4 shows the relative timing. figure 6-4. external reset timing table 6-2. pin bit set timing reset type number of cycl es required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l cgmout reset and system initialization mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 63 6.3.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow resetting of external peripherals. the internal reset signal irst continues to be asserted for an additional 32 cycles. (see figure 6-5 .) an internal reset can be caused by an ille gal address, illegal opcode, cop timeout, lvi, or por. (see figure 6-6 .) note that for lvi or por resets, the sim cycles through 4096 cgmxclk cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 6-5 . figure 6-5. internal reset timing the cop reset is asynchronous to the bus clock. figure 6-6. sources of internal reset the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. 6.3.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. sixty-four cgmxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, these events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables cgmout. internal clocks to the cpu and modules are hel d inactive for 4096 cgmxclk cycles to allow stabilization of the oscillator. the rst pin is driven low during the oscillator stabilization time. the por bit of the sim reset status register (srs r) is set and all other bits in the register are cleared. irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk illegal address rst illegal opcode rst coprst lvi por internal reset system integration module (sim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 64 freescale semiconductor figure 6-7. por recovery 6.3.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of th e cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module timeout, write any value to location $ffff. writing to location $ffff clears the cop counter and bits 12 through 4 of the sim coun ter. the sim counter output, which occurs at least every 2 13 ? 2 4 cgmxclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximu m amount of time before the first timeout. the cop module is disabled if the rst pin or the irq1 pin is held at v dd +v hi while the mcu is in monitor mode. the cop module can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq1 pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v dd +v hi on the rst pin disables the cop module. 6.3.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the mask option register is logic 0, the sim treats the stop instruction as an illegal opcode and causes an i llegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 6.3.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped add ress does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff sim counter mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 65 6.3.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the lvi tripf voltage. the lvi bit in the sim reset status r egister (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 40 96 cgmxclk cycles. sixty-four cgmxclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. note the mc68hc(9)08lk60 does not have an lvi module. 6.4 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly mo dule (cop). the sim counter overflow supplies the clock for the cop module. the sim counter is 13 bits long and is clock ed by the falling edge of cgmxclk. 6.4.1 sim counter during power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initializ ed, it enables the clock generation module (cgm) to drive the bus clock state machine. 6.4.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the mask option register. if the ssrec bit is a logic 1, then t he stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32 cgmxclk cycles. this is ideal for applications using canned oscillators that do not require long startup times from stop mode. external crys tal applications should use the full stop recovery time, that is, with ssrec cleared. note the mc68hc(9)08lk60 does not allow stop mode operation. 6.4.3 sim counter and reset states external reset has no effect on the sim counter. (see 6.6.2 stop mode for details.) the sim counter is free-running after all reset states. (see 6.3.2 active resets from internal sources for counter control and internal reset recovery sequences.) 6.5 exception control normal, sequential program execution can be changed in three different ways: interrupts: ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts system integration module (sim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 66 freescale semiconductor 6.5.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 6-8 shows interrupt entry timing. figure 6-9 shows interrupt recovery timing. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt may take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared). (see figure 6-10 .) figure 6-8 . interrupt entry figure 6-9. interrupt recovery module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[7:0] pc ? 1[15:8] opcode operand i bit exception control mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 67 figure 6-10. interrupt processing no no no yes no no yes no yes yes as many interrupts i bit set? from reset break interrupt? i bit set? irq0 interrupt? irq1 interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes yes as exist on the chip system integration module (sim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 68 freescale semiconductor 6.5.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 6-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt servic e routine, the pending interrupt is serviced before the lda instruction is executed. figure 6-11 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. 6.5.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine low-power modes mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 69 6.5.2 reset all reset sources always have equal and highest priority and cannot be arbitrated. 6.5.3 break interrupts the break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. (see chapter 9 break module .) the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 6.5.4 status flag pr otection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from bei ng cleared by properly initializing the break clear flag enable bit (bcfe) in the sim break flag control register (sbfcr). protecting flags in break mode ensures that set fl ags will not be cleared while in break mode. this protection allows registers to be freely read and writ ten during break mode without losing status flag information. setting the bcfe bit enables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status fl ags with a 2-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 6.6 low-power modes executing the wait or stop instruction puts the mcu in a low-power-consumption mode for standby situations. the sim holds the cpu in a non-clocked st ate. the operation of each of these modes is described in the following paragraphs. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. note the mc68hc(9)08lk60 does not allow stop mode operation. 6.6.1 wait mode in wait mode, the cpu clocks are inactive while the peripheral clocks continue to run. figure 6-12 shows the timing for wait mode entry. a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wa it instruction during which the interrupt occurred. in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode also can be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in the mask option register is logic 0, then the computer operating properly module (cop) is enabled and remains active in wait mode. system integration module (sim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 70 freescale semiconductor figure 6-12. wait mode entry timing figure 6-13 and figure 6-14 show the timing for wait recovery. figure 6-13. wait recovery from interrupt or break figure 6-14. wait recovery from internal reset 6.6.2 stop mode note the mc68hc(9)08lk60 does not allow stop mode operation. in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. the sim disables the clock generator module outputs (cgmout and cgmxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in the mask option register (mor). if ssrec is set, stop recovery is reduce d from the normal delay of 4096 cgmxclk cycles down to 32. this is ideal for applications using canned os cillators that do not require long startup times from stop mode. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles sim registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 71 note external crystal applications should use the full stop recovery time by clearing the ssrec bit. a break interrupt during stop mode sets the sim break stop/wait bit (sbsw) in the sim break status register (sbsr). the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 6-15 shows stop mode entry timing. figure 6-15. stop mode entry timing figure 6-16. stop mode recovery from interrupt or break 6.7 sim registers the sim has three memory mapped registers. table 6-3 shows the mapping of these registers. table 6-3. sim registers address register access mode $fe00 sbsr ? sim break status register user $fe01 srsr ? sim reset status register user $fe03 sbfcr ? sim break flag control register user stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. cgmxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period system integration module (sim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 72 freescale semiconductor 6.7.1 sim break status register the sim break status register contains a flag to indica te that a break caused an exit from stop or wait mode. sbsw ? sim break stop/wait bit this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. reset clears sbsw. 1 = stop mode or wait mode was exited by break interrupt. 0 = stop mode or wait mode was not exited by break interrupt. sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. the following code is an example of this. writing 0 to the sbsw bit clears it. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a logic 0 clears sbsw. figure 6-17. sim break status register (sbsr) ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ; if returnlo is not zero, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte, too. dolo dec lobyte,sp ; point to wait/stop opcode. return pulh rti ; restore h register. sim registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 73 6.7.2 sim reset status register this register contains six flags that show the source of the last reset. clear the sim reset status register by reading it. a power-on reset sets the por bi t and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ? low-voltage inhibit reset bit 1 = last reset caused by the lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 = unimplemented figure 6-18. sim reset status register (srsr) system integration module (sim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 74 freescale semiconductor 6.7.3 sim break flag control register the sim break control register contains a bit that e nables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 6-19. sim break flag control register (sbfcr) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 75 chapter 7 clock generator module (cgmb) 7.1 introduction this section describes the clock generator module (cgm, version b). the cgm generates the crystal clock signal, cgmxclk, which operates at the fre quency of the crystal. the cgm also generates the base clock signal, cgmout, from which the system in tegration module (sim) derives the system clocks. cgmout is based on either the crystal clock divide d by two or the phase-locked loop (pll) clock, cgmvclk, divided by two. the pll is a fully functional frequency generator designed for use with crystals or ceramic resonators. the pll can generate a 4-mhz bus frequency without using a 16-mhz crystal. 7.2 features features of the cgmb include: phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal reference low-frequency crystal operation with low-power operation and high-output frequency resolution programmable reference divider for even greater resolution programmable prescaler for power-of-two increases in frequency programmable hardware voltage-controlled oscillator (vco) for low-jitter operation automatic bandwidth control mode for low-jitter operation automatic frequency lock detector cpu interrupt on entry or exit from locked condition 7.3 functional description the cgmb consists of three major submodules: crystal oscillator circuit ? the crystal oscillat or circuit generates the constant crystal frequency clock, cgmxclk. phase-locked loop (pll) ? the pll generates the programmable vco frequency clock, cgmvclk. base clock selector circuit ? this software-cont rolled circuit selects either cgmxclk divided by two or the vco clock, cgmvclk, divided by two as the base cl ock, cgmout. the sim derives the system clocks from cgmout. figure 7-1 shows the structure of the cgm. clock generator module (cgmb) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 76 freescale semiconductor figure 7-1. cgmb block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator automatic mode control lock detector clock cgmxclk cgmout cgmvdv cgmvclk simoscen crystal oscillator interrupt control cgmint cgmrdv pll analog 2 cgmrclk osc2 osc1 select circuit v dda cgmxfc v ssa lock auto acq vpr[1:0] pllie pllf mul[11:0] reference divider rds[3:0] vrs[7:0] frequency divider pre[1:0] functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 77 7.3.1 crystal os cillator circuit the crystal oscillator circuit consists of an inverting am plifier and an external crystal. the osc1 pin is the input to the amplifier and the osc2 pin is the out put. the simoscen signal from the system integration module (sim) enables the crystal oscillator circuit. the cgmxclk signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cgmxclk is then buffered to pr oduce cgmrclk, the pll reference clock. cgmxclk can be used by other modules which require precise timing for operation. the duty cycle of cgmxclk is not guaranteed to be 50% and depends on ex ternal factors, including the crystal and related external components. an externally generated clock also can feed the osc1 pin of the crystal osci llator circuit. connect the external clock to the osc1 pin and let the osc2 pin float. 7.3.2 phase-locked loop circuit (pll) the pll is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. the pll can change between acquisition and tracking modes either automatically or manually. 7.3.2.1 pll circuits the pll consists of: voltage-controlled oscillator (vco) reference divider frequency prescaler modulo vco frequency divider phase detector loop filter lock detector the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, incl uding supply and cgmxfc noise. the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cgmxfc pin changes the frequency wi thin this range. by design, f vrs is equal to the nominal center-of-range frequency, f nom , (38.4 khz) times a linear factor, l, and a power-of-two factor, e, or (l 2 e )f nom . cgmrclk is the pll reference clock, a buffered ve rsion of cgmxclk. cgmrclk runs at a frequency, f rclk , and is fed to the pll through a programmabl e modulo reference divi der, which divides f rclk by a factor r. this feature allows frequency steps of higher resolution. the divider?s output is the final reference clock, cgmrdv, running at a frequency f rdv =f rclk /r. the vco?s output clock, cgmvclk, running at a frequency f vclk , is fed back through a programmable prescale divider and a programmable modulo divi der. the prescaler divides the vco clock by a power-of-two factor, p, and the modulo divider reduces the vco clock by a factor, n. the divider?s output is the vco feedback clock, cgmvdv, running at a frequency f vdv =f vclk /(n 2 p ). (see 7.3.2.4 programming the pll for more information.) the phase detector then compares the vco feedback cloc k, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase difference between the two signals. the clock generator module (cgmb) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 78 freescale semiconductor loop filter then slightly alters the dc voltage on the external capacitor co nnected to cgmxfc based on the width and direction of the correction pulse. the fi lter can make fast or slow corrections depending on its mode, described in 7.3.2.2 acquisition and tracking modes . the value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the frequencies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to the final reference frequency f rdv . the circuit determines the mode of the pll and the lock condition based on this comparison. 7.3.2.2 acquisition and tracking modes the pll filter is manually or automatically configurable into one of two operating modes: acquisition mode ? in acquisition mode, the filt er can make large frequency corrections to the vco. this mode is used at pll start-up or when the pll has suffered a severe noise hit and the vco frequency is far off the desired freq uency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register. (see 7.5.2 pll bandwidth control register .) tracking mode ? in tracking mode, the filter makes only small corrections to the frequency of the vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode when the vco frequency is nearly correct, such as when the pll is selected as the base clock source. (see 7.3.3 base clock selector circuit .) the pll is in tracking mode automatically when not in acquisition mode or when the acq bit is set. 7.3.2.3 manual and automatic pll bandwidth modes the pll can change the bandwidth or operational mode of the loop filter manua lly or automatically. in automatic bandwidth control mode (auto = 1), th e lock detector automatically switches between acquisition and tracking modes. automatic bandwidth c ontrol mode also is used to determine when the vco clock, cgmvclk, is safe to use as th e source for the base clock, cgmout. (see 7.5.2 pll bandwidth control register .) if pll interrupts are enabled, the software can wait for a pll interrupt request and then check the lock bit. if interrupts are disabled, software can poll the lock bit continuously (during pll startup, usually ) or at periodic intervals. in either case, when the lock bit is set, the vco clock is safe to use as the source for the base clock. (see 7.3.3 base clock selector circuit .) if the vco is selected as the source for the base clock and the lock bit is clear, the pll has suffered a severe noise hit and the software must take appr opriate action, depending on the application. (see 7.6 interrupts for information and precautions on using interru pts.) these conditions apply when the pll is in automatic bandwidth control mode: the acq bit (see 7.5.2 pll bandwidth control register ) is a read-only indicator of the mode of the filter. (see 7.3.2.2 acquisition and tracking modes .) the acq bit is set when the vco frequency is within a certain tolerance, ? trk , and is cleared when the vco frequency is out of a certain tolerance, ? unt . (see 7.9 acquisition/lock time specifications for more information.) the lock bit is a read-only indica tor of the locked state of the pll. the lock bit is set when the vco freq uency is within a certain tolerance, ? lock , and is cleared when the vco frequency is out of a certain tolerance, ? unl . (see 7.9 acquisition/lock time specifications for more information.) cpu interrupts can occur if enabled (pllie = 1) when the pll?s lock c ondition changes, toggling the lock bit. (see 7.5.1 pll control register .) functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 79 the pll also may operate in manual mode (auto = 0) . manual mode is used by systems that do not require an indicator of the lock condition for proper operation. such systems typically operate well below f busmax and require fast startup. these conditions apply when in manual mode: acq is a writable control bit that controls the mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. before entering tracking mode (acq = 1), software must wait a given time, t acq (see 7.9 acquisition/lock time specifications ), after turning on the pll by setting pllon in the pll control register (pctl). software must wait a given time, t al , after entering tracking mode before selecting the pll as the clock source to cgmout (bcs = 1). the lock bit is disabled. cpu interrupts from the cgmb are disabled. 7.3.2.4 programming the pll this procedure shows how to program the pll. note the round function in the following equations means that the real number should be rounded to the nearest integer number. 1. choose the desired bus frequency, f busdes . 2. calculate the desired vco frequency (f our times the desired bus frequency). 3. choose a practical pll reference frequency, f rclk . 4. select the prescaler power-of-two multiplier, p. 5. select the reference divider based on the resolution desired. for maximum resolution, use the formula below. however, higher degrees of resolu tion slow down the final reference frequency, which may cause acquisition time to increase and may affect the value of the external capacitor. for more information, see 7.9 acquisition/lock time specifications . f vclkdes 4f busdes = p integer 2 pmax f vclkdes f vclkmax ----------------------------------------------------------- - ?? ?? ?? ?? log 2 () log ------------------------------------------------------------------------- - 1 + = r round r max f vclkdes 2 p f rclk -------------------------------- ?? ?? ?? ?? integer f vclkdes 2 p f rclk -------------------------------- ?? ?? ?? ?? ? ?? ?? ?? ?? ?? = clock generator module (cgmb) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 80 freescale semiconductor select a vco frequency multiplier, n. 6. for fastest acquisition time, reduce n/r until r is the smallest value possible. for example, if n = 6 and r = 4, n reduces to 3 and r reduces to 2. 7. calculate and verify the adequacy of the vco and bus frequencies f vclk and f bus . 8. select the vco?s power-of-two range multiplier, e. higher values of e should be used at higher frequencies. select a vco linear range multiplier, l, where f nom = 38.4 khz 9. calculate and verify the adequacy of the vco programmed center-of-range frequency f vrs . f vrs = (l 2 e )f nom 10. verify the choice of p, r, n, e, and l by comparing f vclk to f vrs and f vclkdes . for proper operation, f vclk must be within the application?s tolerance of f vclkdes , and f vrs must be as close as possible to f vclk . note exceeding the recommended maximum bus frequency or vco frequency can crash the mcu. 11. program the pll registers accordingly: a. in the pre bits of the pll control r egister, program the binary equivalent of p. b. in the vpr bits of the pll control r egister, program the binary equivalent of e. c. in the pll multiplier select register low and t he pll multiplier select register high, program the binary equivalent of n. d. in the pll vco range select register, program the binary coded equivalent of l. e. in the pll reference divider select register, program the binary coded equivalent of r. n round rf vclkdes 2 p f rclk ------------------------------------------ ?? ?? ?? ?? = f vclk nf rclk = f vclk 2 p nr ? () f rclk = f bus f vclk () 4 ? = e integer 2 emax f vclk f vrsmax ---------------------------------------------- ?? ?? ?? ?? log 2 () log ------------------------------------------------------------ 1 + = l round f vclk 2 e f nom ------------------------------ ?? ?? ?? ?? = functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 81 refer to table 7-1 for a numeric example with numbers in hexadecimal notation. note the numeric examples given in table 7-1 assume a crystal frequency of 38.4 khz. 7.3.2.5 special programming exceptions the programming method described in 7.3.2.4 programming the pll does not account for three possible exceptions. a value of 0 for r, n, or l is meaningless when used in the equations given. to account for these exceptions: a 0 value for r or n is interpreted exactly the same as a value of one at the minimum frequency and the vco range power-of-two bits. a 0 value for l disables the pll and prevents its selection as the source for the base clock. (see 7.3.3 base clock selector circuit .) 7.3.3 base clock se lector circuit this circuit is used to select either the crystal cl ock, cgmxclk, or the vco clock, cgmvclk, as the source of the base clock, cgmout. the two input cl ocks go through a transition c ontrol circuit that waits up to three cgmxclk cycles and three cgmvclk cycles to change from one clock source to the other. during this time, cgmout is held in stasis. the outpu t of the transition control circuit is then divided by two to correct the duty cycle. therefore, the bus cl ock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll control register (pctl) selects which clock drives cgmout. the vco clock cannot be selected as the base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be turned on or off simultaneously with the selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the factor l is programmed to a 0. this value would set up a condition inconsistent with the operation of the pll, so that the pll would be disabled and the crysta l clock would be forced as the source of the base clock. table 7-1. numeric example of pll register programming bus frequency e p n l r 307,200 hz 1 1 10 10 1 614,400 hz 1 1 20 20 1 652,800 hz 2 2 11 11 1 691,200 hz 2 2 12 12 1 729,600 hz 2 2 13 13 1 768,000 hz 2 2 14 14 1 806,400 hz 2 2 15 15 1 998,400 hz 2 2 1a 1a 1 clock generator module (cgmb) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 82 freescale semiconductor 7.3.4 cgmb external connections in its typical configuration, the cgmb requires se ven external components. five of these are for the crystal oscillator and two are for the pll. the crystal oscillator normally is connected in a pierce oscillator configuration, as shown in figure 7-2 . figure 7-2 shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. refer to the crystal manufacturer?s data for more information. figure 7-2 also shows the external components for the pll: bypass capacitor, c byp filter capacitor, c f routing should be done with great care to minimize signal cross talk and noise. figure 7-2. cgmb external connections c 1 c 2 c f simoscen cgmxclk r b x 1 r s * c byp osc1 osc2 v clock generator module (cgmb) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 84 freescale semiconductor 7.4.8 cgmb base clock output (cgmout) cgmout is the clock output of the cgmb. this signal goes to the sim, which generates the mcu clocks. cgmout is a 50% duty cycle clock running at twice the bus frequency. cgmout is software programmable to be either the oscillator output, cg mxclk, divided by two or the vco clock, cgmvclk, divided by two. 7.4.9 cgmb cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector. 7.5 cgmb registers these registers control and monitor operation of the cgmb: pll control register (see 7.5.1 pll control register ) pll bandwidth control register (see 7.5.2 pll bandwidth control register ) pll multiplier select register high (see 7.5.3 pll multiplier select register high ) pll multiplier select register low (see 7.5.4 pll multiplier select register low ) pll vco range select register (see 7.5.5 pll vco range select register ) pll reference divider select register (see 7.5.6 pll reference divider select register ) figure 7-3 provides a summary of the cgmb registers. addr. name bit 7654321bit 0 $0007 pll control register (pctl) read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset:00101111 $0008 pll bandwidth control register (pbwc) read: auto lock acq 0000 r write: reset:00000000 $0009 pll multiplier select register high (pmsh) read: 0 0 0 0 mul11 mul10 mul9 mul8 write: reset:00000000 $000a pll multiplier select register low (pmsl) read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 $000b pll vco range select register (pvrs) read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 $000c pll reference divider select register (prds) read: 0 0 0 0 rds3 rds2 rds1 rds0 write: reset:00000001 = unimplemented r = reserved figure 7-3. cgmb i/o register summary cgmb registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 85 7.5.1 pll control register the pll control register (pctl) contains the inte rrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the vco power of two range selector bits. pllie ? pll interrupt enable bit this read/write bit enables the pll to generate an interrupt request when the lock bit toggles, setting the pll flag, pllf. when the auto bit in the pll b andwidth control register (pbwc) is clear, pllie cannot be written and reads as logic 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ? pll interrupt flag bit this read-only bit is set whenever the lock bit toggles. pllf generates an interrupt request if the pllie bit also is set. pllf always reads as logic 0 when the auto bit in the pll bandwidth control register (pbwc) is clear. clear the pllf bit by readi ng the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note do not inadvertently clear the pllf bit. any read or read-modify-write operation on the pll control register clears the pllf bit. pllon ? pll on bit this read/write bit activates the pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving t he base clock, cgmout (bcs = 1). (see 7.3.3 base clock selector circuit .) reset sets this bit so that the l oop can stabilize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit selects either the crystal oscillator output, cgmxclk, or the vco clock, cgmvclk, as the source of the cgm output , cgmout. cgmout frequency is one-half the frequency of the selected clock. bcs cannot be set while the pllon bit is clear. after toggling bcs, it may take up to three cgmxclk and three cgmv clk cycles to complete the transition from one source clock to the other. during the transit ion, cgmout is held in stasis. (see 7.3.3 base clock selector circuit .) reset clears the bcs bit. 1 = cgmvclk divided by two drives cgmout 0 = cgmxclk divided by two drives cgmout address: $0007 bit 7654321bit 0 read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset:00101111 = unimplemented figure 7-4. pll control register (pctl) clock generator module (cgmb) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 86 freescale semiconductor note pllon and bcs have built-in protecti on that prevents the base clock selector circuit from selecting the vco clock as the source of the base clock if the pll is off. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is cl ear. if the pll is off (pllon = 0), selecting cgmvclk requires two writes to the pll control register. (see 7.3.3 base clock selector circuit .) pre1 and pre0 ? prescaler program bits these read/write bits control a prescaler that selects the prescaler power-of-two multiplier, p. (see 7.3.2.1 pll circuits and 7.3.2.4 programming the pll .) pre1 and pre0 cannot be written when the pllon bit is set. reset clears these bits. vpr1 and vpr0 ? vco power-of-two range select bits these read/write bits control the vco?s hardware power-of-two range multiplier, e, that, in conjunction with l (see 7.3.2.1 pll circuits , 7.3.2.4 programming the pll , and 7.5.5 pll vco range select register .) controls the hardware center-of-range frequency, f vrs . vpr1 and vpr0 cannot be written when the pllon bit is set. reset clears these bits. table 7-2. pre1 and pre0 programming pre1 and pre0 p prescaler multiplier 00 0 1 01 1 2 10 2 4 11 3 8 table 7-3. vpr1 and vpr0 programming vpr1 and vpr0 e vco power-of-two range multiplier 00 0 1 01 1 2 10 2 4 11 3 8 cgmb registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 87 7.5.2 pll bandwidth control register the pll bandwidth control register (pbwc): selects automatic or manual (softw are-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode, indicates wh en the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode auto ? automatic bandwidth control bit this read/write bit selects automatic or manual b andwidth control. when initializing the pll for manual operation (auto = 0), clear the acq bit before turning on the pll. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is locked (running at the programmed frequency). when the auto bit is clear, lock reads as logic 0 and has no meaning. note the write function of this bit is reserved for test, so this bit must always be written a 0. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency incorrect or unlocked acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tracking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisition or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. reset clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode address: $0008 bit 7654321bit 0 read: auto lock acq 0000 r write: reset:00000000 = unimplemented r = reserved figure 7-5. pll bandwidth control register (pbwc) clock generator module (cgmb) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 88 freescale semiconductor 7.5.3 pll multiplier select register high the pll multiplier select register high (pmsh) cont ains the programming informat ion for the high byte of the modulo feedback divider. mul11?mul8 ? multiplier select bits these read/write bits control the high byte of the modulo feedback divider that selects the vco frequency multiplier n. (see 7.3.2.1 pll circuits and 7.3.2.4 programming the pll .) a value of $0000 in the multiplier select registers configures the modulo feedback divider the same as a value of $0001. reset initializes the registers to $0040, for a default multiply value of 64. note the multiplier select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1). 7.5.4 pll multiplier select register low the pll multiplier select register (pmsl) low contains the programming information for the low byte of the modulo feedback divider. mul7?mul0 ? multiplier select bits these read/write bits control the low byte of the modulo feedback divider that selects the vco frequency multiplier, n. (see 7.3.2.1 pll circuits and 7.3.2.4 programming the pll .) mul7?mul0 cannot be written when the pllon bit in the pctl is set. a value of $0000 in the multiplier select registers configures the modulo feedback divider t he same as a value of $0001. reset initializes the register to $40, for a default multiply value of 64. note the multiplier select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1). address: $0009 bit 7654321bit 0 read:0000 mul11 mul10 mul9 mul8 write: reset:00000000 = unimplemented figure 7-6. pll multiplier select register high (pmsh) address: $000a bit 7654321bit 0 read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 figure 7-7. pll multiplier select register low (pmsl) cgmb registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 89 7.5.5 pll vco r ange select register the pll vco range select register (pvrs) contai ns the programming information required for the hardware configuration of the vco. vrs7?vrs0 ? vco range select bits these read/write bits control the hardware center-of -range linear multiplier l which, in conjunction with e (see 7.3.2.1 pll circuits , 7.3.2.4 programming the pll , and 7.5.1 pll control register ), controls the hardware center-of-range frequency, f vrs . vrs7?vrs0 cannot be writt en when the pllon bit in the pctl is set (see 7.3.2.5 special programming exceptions ). a value of $00 in the vco range select register disables the pll and clears the bcs bit in the pll control register. (see 7.3.3 base clock selector circuit and 7.3.2.5 special programming exceptions .) reset initializes the register to $40 for a default range multiply value of 64. note the vco range select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1) and such that the vco clock cannot be selected as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the pll vco range select register must be programmed correctly. incorrect programming may result in failure of the pll to achieve lock. 7.5.6 pll reference di vider select register the pll reference divider select register (prds) contains the programming information for the modulo reference divider. rds3?rds0 ? reference divider select bits these read/write bits control the modulo reference divi der that selects the reference division factor r. (see 7.3.2.1 pll circuits and 7.3.2.4 programming the pll .) rds7?rds0 cannot be written when the pllon bit in the pctl is set. address: $000b bit 7654321bit 0 read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 figure 7-8. pll vco range select register (pvrs) address: $000c bit 7654321bit 0 read:0000 rds3 rds2 rds1 rds0 write: reset:00000000 = unimplemented figure 7-9. pll reference divider select register (prds) clock generator module (cgmb) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 90 freescale semiconductor a value of $00 in the reference divider select register configures the reference divider the same as a value of $01. (see 7.3.2.5 special programming exceptions .) reset initializes the register to $01, for a default divide value of 1. note the reference divider select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1). 7.6 interrupts when the auto bit is set in the pll bandwidth c ontrol register (pbwc), the pll can generate a cpu interrupt request every time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts are enabled or not. when the auto bit is clear, cpu interrupts from the pll are disabled and pllf reads as logic 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit from lock. when the pll enters lock, the vco clock, cgmvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt, and appropriate precautions should be taken. if the application is not frequency-sensitive, interrupts should be disabled to prevent pll interrupt service routines from impeding software performance or from exceeding stack limitations. note software can select the cgmvclk divi ded by two as the cgmout source even if the pll is not locked (lock = 0). therefore, software should make sure the pll is locked before setting the bcs bit. 7.7 wait mode the wait instruction put the mcu in low power-consumption standby mode. the wait instruction does not affect the cgmb. be fore entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl). less power-sensitive applications can dis engage the pll without turning it off. applications that require the pll to wake the mcu from wait mode also can deselect the pll output without turning off the pll. 7.8 cgmb during break interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see 6.7.3 sim break flag control register .) to allow software to clear status bits during a break in terrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it rema ins cleared when the mcu exits the break state. to protect the pllf bit during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write the pll cont rol register during the break state without affecting the pllf bit. acquisition/lock ti me specifications mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 91 7.9 acquisition/lock time specifications the acquisition and lock times of the pll are, in many applications, the most critical pll design parameters. proper design and use of the pll ensure s the highest stability and lowest acquisition/lock times. 7.9.1 acquisition/lock time definitions typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually sp ecified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. therefore, the reaction time is constant in this definition, regardless of the size of the step input. for example, consider a system with a 5% acquisition time tolerance. if a command instructs the system to change from 0 hz to 1 mhz, the acquisition time is the time taken for the frequency to reach 1 mhz 50 khz. fifty khz = 5% of the 1-mhz step input. or, if the system is operating at 1 mhz and suffe rs a ?100 khz noise hit, the acquisition time is the time taken to return from 900 khz to 1 mhz 5 khz. five khz = 5% of the 100-khz step input. other systems refer to acquisition and lock times as t he time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. therefore, the acquisition or lock time varies according to the original error in the output. minor errors may not even be registered. typical pll applications prefer to use this definition beca use the system requires the output frequency to be within a certain tolerance of the desired frequenc y regardless of the size of the initial error. the discrepancy in these definitions makes it difficul t to specify an acquisition or lock time for a typical pll. therefore, the definitions for acquisition and lock times for this module are as follows: acquisition time, t acq , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance, ? trk . acquisition time is based on an initial frequency error, (f des ? f orig )/f des , of not more than 100%. in automatic bandwidth control mode (see 7.3.2.3 manual and automatic pll bandwidth modes ), acquisition time expires when the acq bit becomes set in the pll bandwidth control register (pbwc). lock time, t lock , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance, ? lock . lock time is based on an initial frequency error, (f des ? f orig )/f des , of not more than 100%. in automatic bandwidth control mode, lock time expires when the lock bit becomes set in the pll bandwidth control register (pbwc). (see 7.3.2.3 manual and automatic pll bandwidth modes .) obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases. 7.9.2 parametric in fluences on reaction time acquisition and lock times are designed to be as short as possible while still pr oviding the highest possible stability. these reaction times are not constant, however . many factors directly and indirectly affect the acquisition time. the most critical parameter which affects the reacti on times of the pll is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corrections. for stability, the corrections must be small compared to the desired frequency, so several corrections are clock generator module (cgmb) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 92 freescale semiconductor required to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is also under user control via the choice of crystal frequency f xclk and the r value programmed in the reference divider. (see 7.3.2.1 pll circuits , 7.3.2.4 programming the pll , and 7.5.6 pll reference divider select register ). another critical parameter is the external filter capacitor. the pll modifies the voltage on the vco by adding or subtracting charge from this capacitor. therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is pr oportional to the capacitor size. the size of the capacitor also is related to the stability of the pll. if the capacitor is too small, the pll cannot make small enough adjustments to the voltage and the system cannot lock. if the capacitor is too large, the pll may not be able to adjust the voltage in a reasonable time. (see 7.9.3 choosing a filter capacitor .) also important is the operating voltage potential applied to v dda . the power supply potential alters the characteristics of the pll. a fixed value is best. va riable supplies, such as batteries, are acceptable if they vary within a known range at very slow sp eeds. noise on the power s upply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the pll. temperature and processing also can affect acquisition time because the electrical characteristics of the pll change. the part operates as spec ified as long as thes e influences stay within the specified limits. external factors, however, can caus e drastic changes in the operation of the pll. these factors include noise injected into the pll through the filter capacito r, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 7.9.3 choosing a filter capacitor as described in 7.9.2 parametric influences on reaction time , the external filter capacitor, c f , is critical to the stability and reaction time of the pll. t he pll also is dependent on reference frequency and supply voltage. the value of the capacitor must, theref ore, be chosen with supply potential and reference frequency in mind. for proper operation, the external filter capacitor must be chosen according to this equation: for acceptable values of c fact , see 7.9 acquisition/lock time specifications . for the value of v dda , choose the voltage potential at which the mcu is operating. if the power supply is variable, choose a value near the middle of the range of possible supply values. this equation does not always yield a commonly av ailable capacitor size, so round to the nearest available size. if the value is between two different sizes, choose the higher value for better stability. choosing the lower size may seem attractive for acquisition time improvement, but the pll may become unstable. also, always choose a ca pacitor with a tight tolerance ( 20% or better) and low dissipation. c f c fact v dda f rdv ----------------- ?? ?? ?? = acquisition/lock ti me specifications mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 93 7.9.4 reaction ti me calculation the actual acquisition and lock times can be calculated using the equations here. these equations yield nominal values under the following conditions: correct selection of filter capacitor, c f (see 7.9.3 choosing a filter capacitor ) room temperature operation negligible external leakage on cgmxfc negligible noise the k factor in the equations is derived from internal pll parameters. k acq is the k factor when the pll is configured in acquisition mode, and k trk is the k factor when the pll is configured in tracking mode. (see 7.3.2.2 acquisition and tracking modes .) note the inverse proportionality between the lock time and the reference frequency. in automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the reference frequency. (see 7.3.2.3 manual and automatic pll bandwidth modes .) a certain number of clock cycles, n acq , is required to ascertain that the pll is within the tracking mode entry tolerance, ? trk , before exiting acquisition mode. a certain number of clock cycles, n trk , is required to ascertain that the pll is within the lock mode entry tolerance, ? lock . therefore, the acquisition time, t acq , is an integer multiple of n acq /f rdv , and the acquisition to lock time, t al , is an integer multiple of n trk /f rdv . also, since the average frequency over the entire measurement perio d must be within the specified tolerance, the total time usually is longer than t lock as calculated above. in manual mode, it is usually necessary to wait considerably longer than t lock before selecting the pll clock (see 7.3.3 base clock selector circuit ), because the factors described in 7.9.2 parametric influences on reaction time may slow the lock time considerably. t acq v dda f rdv ----------------- ?? ?? ?? 8 k acq ----------------- ?? ?? = t al v dda f rdv ----------------- ?? ?? ?? 4 k trk ---------------- ?? ?? = t lock t acq t al + = clock generator module (cgmb) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 94 freescale semiconductor mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 95 chapter 8 functional controller module (fcm) 8.1 introduction the fcm provides timekeeping fu nctions and the software computer operating properly (cop) mechanism. 8.2 features features of the fcm include: real-time clock with seconds, minutes, and hours counters software chronograph counter watchdog timer alarm clock with interrupts 8.3 functional description the functional controller module (fcm ) includes several of the functional controller circuits traditionally designed into custom mcus for paging applications. this module is specifically ta rgeted for use with the hc08 cpu. the circuits included are: real-time clock (rtc) interrupts with chronograph register watchdog timer, also called the computer operating properly (cop) timer time base circuit which supports 32.000-khz and 38.400-khz crystal oscillators in addition to these two crystal options, a provision to use a crystal with a frequency two times these frequencies has been created. this was designed specific ally for use with a 76.8- khz crystal oscillator. this module provides nine registers for software cont rol. the clock source of the rtc interrupts and status registers are synchronized to the bus timing to ensure synchronous register access. 8.4 module description the functional controller module is an hc08-compatible module designed for use in paging applications. it connects to the hc08 internal bus and communicate s to the hc08 cpu by way of the address bus, data bus, and control signals. the crystal oscillator si gnal (cgmxclk) enters the module and connects to the timebase circuit. the timebase creates cl ock signals which feed the real-time clock. functional controller module (fcm) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 96 freescale semiconductor figure 8-1. functional controller block diagram 8.4.1 timebase submodule the timebase submodule is designed to create timing signals equivalent to any binary division of the crystal oscillator frequency. clock signals created at frequencies of 1 hz, 2 hz, and 4 hz are fed to the real-time clock (rtc) submodule. when a frequency of 4 hz is selected, the frequency will vary from 5 hz to 3.3 hz with an average of 4 hz. the timebase circuit also generates a 100-hz clock signal which is fed to the rtc to produce a software chronograph function. in addition, two signals (1 khz and 2 khz) are created for use by other mcu modules. software selectable options are available to support the use of a 32.000-khz or 38.400-khz crystal oscillator. the default option is for 38.400 khz. t12 and t23 reset timebase system address/data bus /control signals interrupt interface to sim 1000 hz cgmxclk timebase buffers timer watchdog to sim 2000 hz; to lcd reset control register chrono clock system chrono data register seconds data register minutes data counter and alarm register hours data counter and alarm register rtc control register rtc status register module description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 97 figure 8-2. real-time clock system block diagram 8.4.2 real-tim e clock submodule the rtc module consists of the rtc control register , the chronograph data register, the hours, minutes, and seconds registers for timekeeping, and the hours and minutes alarm registers. the real-time clock (rtc) system will provide a periodic interrupt to t he cpu of 1 hour, 1 minute, 1 second, 1 hz, 2 hz, or 4 hz for software timekeeping functions and an interr upt with 10 hz resolution which can be used to generate chronometer functions in software. when a a per iodic interrupt of 4 hz is selected, the periodic interrupt will vary from 5 hz to 3.3 hz with an average of 4 hz. the chronograph data register can be chronograph data register rtc interrupt chronograph interrupt 10 hz 100 hz 1 hz to interrupt logic from timebase circuit 10 hz mux 2 hz 4 hz rtc control register rtc hours counter rtc minutes counter rtc seconds counter 1 hz 1 / 60 hz 1 / 3600 hz interrupt enable enable 1 hour interrupt enable rtc hours alarm rtc minutes alarm 1 minute 1 sec irq functional controller module (fcm) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 98 freescale semiconductor cleared using the chrc bit in the timebase control register. see figure 8-4 . the timebase counter can also be cleared by setting the tbclr in the timebase control register. see figure 8-4 . note this section assumes that a 32.000-khz oscillator or a 38.400-khz oscillator is used, according to the software option selected. these crystals will generate precise interrupts. crystals of a frequency two times these frequencies can also be used to generate accurate rtc clock control. any other oscillator frequency will not provide accurate 100 hz and 1 hz counters. 8.4.3 cop watchdog timer submodule the computer operating properly (cop) or watchdog ti mer subsystem is a software selectable feature which will generate a system reset if not serviced within the specified watchdog timeout period. the watchdog timer counter chain is derived from an output of the timebase circuit. this input signal is divided to give the watchdog timer reset rate selected by the first write to the cop sele ct bits in the timebase control register. a watchdog timer reset is performed by writing any dat a to address $ffff. this will reset the counter chain and begin the timeout countdown again. the watchdog timer counter chain is also cleared when the mcu is in reset. the value of the two watchdog timer rate select bits in the timebase control register (tbcr) determines the watchdog timer timeout rate. these bits can be written only on the firs t write to this register after a reset. if these bits are never written to, the watchdog ti mer reset rate will be set at 1 second when a 32-khz crystal is used (see table 8-1 ). note although these bits default to 0, the user should write to these bits to prevent subsequent writes from changing the timeout rate. a bit set/clear for any bit in this register is executed as a read-modify-write of this register. if used as the first write to this register, further writes to crs[1:0] would not be valid, and the default value would still be set. the cpu clock halts during wait mode, but the oscillat or and the watchdog timer system are still active. the software should exit wait mode to service the watchdog timer system before the cop timeout period. if the stop instruction is executed on an mcu with stop mode enabled, the watchdo g timer circuit will be disabled. the cop timer is enabled when the mcu comes out of reset. note the mc68hc(9)08lk60 does not allow stop mode operation. 8.5 interrupts the rtc submodule is capable of ge nerating interrupts. three different interrupts can be generated by the clock sections of the real-time clock submodule: 1 minute, 1 hz, 2 hz, or 4 hz alarm chronograph, 10 hz these interrupts are enabled by setting the corresponding bit in the rtc control register. i/o signals mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 99 note when an interrupt of 4 hz is selected, the periodic interrupt will vary from 5 hz to 3.3 hz with an average of 4 hz. 8.6 i/o signals the functional controller m odule is connected to the hc08 bus and has no external pins. 8.7 interrupt signals (fcm, cpu, and irq) the interrupt signals provide the capability for sending an interrupt request to the cpu. the fcm has one interrupt line coming out of the fcm to the system integration module and is an or function of the enabled interrupt sources (chronograph alarm, seconds, minutes, hours, or periodic interrupt). 8.8 functional controller registers figure 8-3 provides a summary of the f unctional controller registers. addr. name bit 7654321bit 0 $0035 timebase control register (tbcr) read: rtce 0 chrc crs1 crs0 r tb2x tb0 write: tbclr reset:00000000 $0036 rtc control register (rtccr) read: hrie minie secie chrie chrce alien prq1 prq0 write: reset:00000000 $0037 rtc status register (rtcsr) read: 0 0 prqf horf minf secf aflg chrf write: reset:00000000 $0038 chronograph data register (chrdr) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 $0039 rtc seconds register (secr) read: 0 0 sec5 sec4 sec3 sec2 sec1 sec0 write: reset:00000000 $003a rtc minutes register (minr) read: 0 0 min5 min4 min3 min2 min1 min0 write: reset:00000000 $003b rtc hours register (horr) read: 0 0 0 hor4 hor3 hor2 hor1 hor0 write: reset:00000000 $003c alarm minutes register (alrmr) read: 0 0 am5 am4 am3 am2 am1 am0 write: reset:00000000 $003d alarm hours register (alrhr) read: 0 0 0 ah4 ah3 ah2 ah1 ah0 write: reset:00000000 = unimplemented r = reserved figure 8-3. summary of the functional controller registers functional controller module (fcm) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 100 freescale semiconductor 8.8.1 timebase c ontrol register this timebase control register (tbcr) is a read/writ e register containing control bits for the timebase outputs which feed other circuits. rtce ? real-time clock enable bit when set to 1, the real-time clock counters are enabled. this bit is cleared by reset. note enabling this bit will affect the clock that increments the seconds counter. it is recommended that this write be performed at the start of the reset sequence, to limit any ti ming discrepancies resultin g from the timebase clocks. tbclr ? timebase clear bit when set to 1, the timebase counter chain is cleared. this bit will automatically clear after the timebase clear function has occurred. this bit will always read a 0 and is cleared by reset. note clearing the timebase by setting tbclr will affect all clocks derived from the timebase, including the real-time clock inputs and the lcd. chrc ? chronograph clear bit this bit clears all bits in the chronograph data register and holds it at that state until this bit is cleared by software. 0 = allows chronograph data register to begin counting 1 = clears chronograph data register and holds value at $00 crs1 and crs0 ? cop rate select bit the value of these two bits determines the wa tchdog timer (wdt) timeout rate. these bits can be written only on the first write to this register after reset. if these bits are never written to, the wdt reset rate will be set at one second. note although these bits default to 0, the user should write to these bits to prevent subsequent writes from changing the timeout rate. a bit set/clear for any bit in this regi ster is executed as a read-modify-write of this register. if used as the first wr ite to this register, further writes to crs[1:0] would not be valid, and the default value would be set. address: $0035 bit 7654321bit 0 read: rtce 0 chrc crs1 crs0 r tb2x tb0 write: tbclr reset:00000000 r= reserved figure 8-4. timebase control register (tbcr) functional controller registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 101 note watchdog refresh shortens the minimum cop rates, given in table 8-1 , by 0.0067 seconds for 38.4-k crystal and by 0.008 seconds for 32-k crystal. tb2x ? timebase times 2 bit when set to 1, the timebase counter chain is di vided by two. this bit was added specifically to accommodate the use of the 76.8-khz crystal oscillator. this bit is cleared by reset. note this bit can only be set once following a reset and can be written only on the first write to this register after reset. tbo ? timebase crystal option bit this bit is used to configure the timebase clocks for the crystal oscill ator used to clock the mcu. refer to table 8-2 for the crystal options selected by these bits. this bit is cleared by reset. note the timebase will start up as if t he 38.4-khz option had been chosen until this bit is written to. this bit can only be set once following a reset and can be written only on the first write to this register after reset. it is recommended that this write be performed at the start of the reset sequence, to limit any ti ming discrepancies resultin g from the timebase clocks. table 8-1. watchdog timer timeout rates crs1 and crs0 minimum cop rate @32.000 khz minimum cop rate @38.400 khz 00 1 sec 0.85 sec 01 2 sec 1.7 sec 10 4 sec 3.4 sec 11 8 sec 6.8 sec table 8-2. timebase crystal options tbo crystal (hz) 038,400 132,000 functional controller module (fcm) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 102 freescale semiconductor 8.8.2 rtc control register the rtc control register (rtccr) is a read/write regi ster containing eight control bits. these bits enable the chronograph function and control interrupts asso ciated with the rtc status register flags. hrie ? hours interrupt enable bit this bit controls whether an interrupt is generated w hen the horf bit is set in the rtc status register. 0 = interrupt disabled 1 = interrupt enabled minie ? minutes interrupt enable bit this bit controls whether an interrupt is generated when the minf bit is set in the rtc status register. 0 = interrupt disabled 1 = interrupt enabled secie ? seconds interrupt enable bit this bit controls whether an interrupt is generated w hen the secf bit is set in the rtc status register. 0 = interrupt disabled 1 = interrupt enabled chrie ? chronograph interrupt enable bit this bit controls whether an interrupt is generated wh en the chrf bit is set in the rtc status register. 0 = interrupt disabled 1 = interrupt enabled chrce ? chronograph clock enable bit this bit controls the 100-hz clock signal to the rt c chronograph register. this bit is cleared by reset. 0 = 100-hz signal disabled, rtc chronograph off 1 = 100 hz signal enabled alien ? alarm interrupt enable bit this bit controls whether an interrupt is generated when the aflg bit is set in the rtc status register. 0 = interrupt disabled 1 = interrupt enabled prq1 and prq0 ? rtc periodic interrupt selection bits these bits control which frequency pulse should be s ent from the rtc to generate a periodic interrupt request. this request is sent to the cpu. these bits select periodic interrupts of 1 hz, 2 hz, or 4 hz as shown in table 8-3 . address: $0036 bit 7654321bit 0 read: hrie minie secie chrie chrce alien prq1 prq0 write: reset:00000000 figure 8-5. rtc control register (rtccr) functional controller registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 103 note when a periodic interrupt of 4 hz is selected, the periodic interrupt will vary from 5 hz to 3.3 hz with an average of 4 hz. 8.8.3 rtc status register the rtc status register (rtcsr) is a read-only register containing six status bits. see figure 8-6 . prqf ? periodic interrupt flag prqf is a status bit indicating that the 1 hz, 2 hz, or 4 hz interval has elapsed. when a a periodic interrupt of 4 hz is selected, the periodic interrupt will vary from 5 hz to 3.3 hz with an average of 4 hz. reset clears prqf. a cpu interrupt will be generated if the prq1 and prq0 bits are set in the rtccr. 0 = flag cleared by a read of the rtc status register with the prqf flag set, followed by a read of the rtc control register. both read operations need not be consecutive. 1 = flag automatically set at 1 hz, 2 hz, or 4 hz intervals. when a a periodic interrupt of 4 hz is selected, the periodic interrupt will vary from 5 hz to 3.3 hz with an average of 4 hz. horf ? hours flag horf is a status bit indicating that the hours counter has rolled over. reset clears horf. a cpu interrupt will be generated if the hrie bit is set in the rtccr. 0 = flag cleared by a read of the rtc status register with the horf flag set, followed by a read of the hours register. both read operations need not be consecutive. 1 = flag automatically set at 1-hour intervals minf ? minutes flag minf is a status bit indicating that the minutes counter 1 has rolled over. reset clears minf. a cpu interrupt will be generated if the minie bit is set in the rtccr. 0 = flag cleared by a read of the rtc status register with the minf flag set, followed by a read of the minutes register. both read operations need not be consecutive. 1 = flag automatically set at 1-minute intervals table 8-3. prq1 and prq0 rtc interrupt periods prq1 and prq0 rtc interrupt period 00 rtc interrupt is disabled. 01 rtc interrupt is 1 hz. 10 rtc interrupt is 2 hz. 11 rtc interrupt is 4 hz. address: $0037 bit 7654321bit 0 read: 0 0 prqf horf minf secf aflg chrf write: reset:00000000 = unimplemented figure 8-6. rtc status register (rtcsr) functional controller module (fcm) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 104 freescale semiconductor secf ? seconds flag secf is a status bit indicating that the seconds c ounter 1-hz interval has elapsed. reset clears secf. a cpu interrupt will be generated if the secie bit is set in the rtccr. 0 = flag cleared by a read of the rtc status regist er with the secf flag set, followed by a read of the seconds register. both read operations need not be consecutive. 1 = flag automatically set at 1-hz intervals aflg ? alarm flag aflg is a status bit indicating that the hours count er matches the alarm hours register and the minutes counter matches the alarm minutes register. reset clears aflg. a cpu interrupt will be generated if the alien bit is set in the rtccr. 0 = flag cleared by a read of the rtc status register with the aflg flag set, followed by a read of the alarm minutes register. both read operations need not be consecutive. 1 = flag automatically set at scheduled alarm time chrf ? chronograph flag chrf is a status bit indicating that the chronog raph 10-hz interval has elapsed. a cpu interrupt request will be generated if chrie is set. reset clears chrf. 0 = flag cleared by a read of the rtc status register with the chrf flag set, followed by a read of the chronograph data register. both read operations need not be consecutive. 1 = flag automatically set at 10-hz intervals 8.8.4 chronograph data register the chronograph data register (chrdr) is a read-only register containing the va lue of a counter which is driven by the 100-hz output of the timebase circuit. this counter has a resolution of 1 100 seconds, or 10 ms. the counter rolls over to 0 after reaching $ff. appropriate software must be written to convert the value read from this register in real time. address: $0038 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 8-7. chronograph data register (chrdr) functional controller registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 105 8.8.5 seconds data register the seconds data register (secr) is a read-write regi ster containing the value of a counter which is driven by the 1-hz output of the timebase ci rcuit. only six bits are used in this register, which rolls over to 0 when the count reaches 59. reset clears these bits. once the correct value is set in this register, the register will contain the current time in seconds. 8.8.6 minutes data register the minutes data register (minr) is a read-write regist er containing the value of a counter which is driven by the output of the seconds register. only six bits are used in this register, which rolls over to 0 when the count reaches 59. reset clears these bits. once the correct time is written to this register, it will contain the current time in minutes. 8.8.7 hours data register the hours data register (horr) is a read-write regist er containing the value of a counter which is driven by the output of the minutes register. only five bits are used in this register, which rolls over to 0 when the count reaches 23. reset clears these bits. once the current time is written to this register, it will contain the current time in the 24 hours clock. address: $0039 bit 7654321bit 0 read: 0 0 sec5 sec4 sec3 sec2 sec1 sec0 write: reset:00000000 = unimplemented figure 8-8. seconds data register (secr) address: $003a bit 7654321bit 0 read: 0 0 min5 min4 min3 min2 min1 min0 write: reset:00000000 = unimplemented figure 8-9. minutes data register (minr) address: $003b bit 7654321bit 0 read: 0 0 0 hor4 hor3 hor2 hor1 hor0 write: reset:00000000 = unimplemented figure 8-10. hours data register (horr) functional controller module (fcm) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 106 freescale semiconductor 8.8.8 alarm minutes register the alarm minutes register (alrmr) is a read-write register containing the value for alarm generation used to match with the minutes data register. only si x bits are used in this register. reset clears these bits. 8.8.9 alarm hours register the alarm hours register (alrhr) is a read-write register containing the value for alarm generation used to match with the hours data regist er. only five bits are used in this register. reset clears these bits. address: $003c bit 7654321bit 0 read: 0 0 am5 am4 am3 am2 am1 am0 write: reset:00000000 = unimplemented figure 8-11. alarm minutes register (alrmr) address: $003d bit 7654321bit 0 read: 0 0 0 ah4 ah3 ah2 ah1 ah0 write: reset:00000000 = unimplemented figure 8-12. alarm hours register (alrhr) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 107 chapter 9 break module 9.1 introduction this section describes the break module. the brea k module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. 9.2 features features of the break module include: accessible input/output (i/o) registers during the break interrupt cpu-generated break interrupts software-generated break interrupts computer operating properly (cop ) disabling during break interrupts 9.3 functional description when the internal address bus matches the value writt en in the break address registers, the break module issues a breakpoint signal (bkpt ) to the system integration module (sim). the sim then causes the cpu to load the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). these events can cause a break interrupt to occur: a cpu-generated address (the address in the program counter) matches the contents of the break address registers. software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated address matches the contents of the break address registers, the break interrupt begins after the cpu completes its current instruction. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 9-1 shows the structure of the break module. 9.3.1 flag protection during break interrupts the sim controls whether or not module status bits can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. for further information, see 6.7.3 sim break flag control register and the break interrupts subsection for each module. break module mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 108 freescale semiconductor figure 9-1. break module block diagram 9.3.2 cpu during break interrupts the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc?$fffd; $fefc?$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. 9.3.3 tim during break interrupts a break interrupt stops the timer counter. 9.3.4 cop during break interrupts the cop is disabled during a break interrupt when v dd +v hi is present on the rst pin. addr. name bit 7654321bit 0 $fe0c break address register high (brkh) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $fe0e break status/control register (brkscr) read: brke brka 000000 write: reset:00000000 = unimplemented figure 9-2. break i/o register summary iab[15:8] iab[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high iab[15:0] bkpt to sim break module registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 109 9.4 break module registers three registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) 9.4.1 break status and control register the break status and control register (brkscr) contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break addres s register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled on 16-bit address match brka ? break active bit this read/write status and control bit is set when a break address match occurs . writing a logic 1 to brka generates a break interrupt. clear brka by writing a logic 0 to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 9-3. break status and control register (brkscr) break module mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 110 freescale semiconductor 9.4.2 break address registers the break address registers (brkh and brkl) contai n the high and low bytes of the desired breakpoint address. reset clears the break address registers. 9.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 9.5.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the return address on the stack if sbsw is se t. clear the sbsw bit by writing logic 0 to it. 9.5.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the sim break status register. see 6.7 sim registers . note the mc68hc(9)08lk60 does not allow stop mode operation. address: $fe0c bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 figure 9-4. break address register high (brkh) address: $fe0d bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 9-5. break address register low (brkl) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 111 chapter 10 power-on reset module (por) 10.1 introduction this section describes the power-on reset (por) module (version b). 10.2 functional description the por module provides a known, stable signal to the mcu at power-on. this signal tracks v dd until the mcu generates a feedback signal to indicate that it is properly initialized. at this time, the por drives its output low. the por is not a brown-out detector, low-voltage detector, or glitch detector. v dd at the por must go completely to 0 to reset the mcu. to detect power-loss conditions, use a low-voltage inhibit (lvi) module or other suitable circuit. figure 10-1. por block diagram v dd porlo porhi cntrclr cntrrst notes: 1. porhi goes high at power-up and is cleared when the sim sets cntrclr. 2. signal names are not necessarily accurate. this diagram is for logical illustration only and may not represent actual circuitry. power-on reset module (por) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 112 freescale semiconductor mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 113 chapter 11 external interrupt module (irq) 11.1 introduction this section describes the external interrupt (irq) module, which supports exte rnal interrupt functions. 11.2 features features of the irq module include: two dedicated external interrupt pins, irq1 and irq2 separate irq1 and irq2 interrupt masks irq2 interrupt disable hysteresis buffers 11.3 functional description a logic 0 applied to any of the external inte rrupt pins can latch a cpu interrupt request. figure 11-2 shows the structure of the irq module. interrupt signals on the irq1 pin are latched into the irq1 latch. interrupt signals on the irq2 pin are latched into the irq2 interrupt latch. an interrupt latch remains set until one of the following actions occurs: vector fetch ? a vector fetch automatically gener ates an interrupt acknowledge signal that clears the latch that caused the vector fetch. software clear ? software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (i scr). writing a logic 1 to the ack1 bit clears the irq1 latch. writing a logic 1 to the ack2 bit clears the irq2 interrupt latch. reset ? a reset automatically clears both interrupt latches. addr. register name bit 7 6 5 4 3 2 1 bit 0 $001d irq status and control register (iscr) read: pin2 0 imask2 mode2 irq2dis 0 imask1 mode1 write: ack2 ack1 reset:00000000 = unimplemented figure 11-1. irq i/o register summary mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 114 freescale semiconductor external interrupt module (irq) figure 11-2. irq module block diagram synchronizer ack1 imask1 dq ck clr irq1 interrupt irq1 latch request v dd mode1 note: irq2dis does not prevent the reading of the state of the irq2 pin in the irq status and control register (iscr). ptb7 ptb7ie ptb7 pullup enable ptb0 ptb0ie irq2/kbi interrupt request irq2 ack2 dq ck clr v dd mode2 imask2 pin2 irq2dis irq2/keyboard interrupt latch synchronizer ptb0 pullup enable irq1 functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 115 all of the external interrupt pins are falling- edge-triggered and are software-configurable to be both falling-edge and low-level-triggered. the mode1 bit in the iscr controls the tri ggering sensitivity of the irq1 pin. the mode2 bit controls the triggering sensitivity of the irq2 pin and the keyboard interrupt pins. when an interrupt pin is edge-triggered only, the interr upt latch remains set until a vector fetch, software clear, or reset occurs. when an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of these occur: vector fetch, software clear, or reset return of the interrupt pin to logic 1 the vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. when set, the imask1 and imask2 bits in the iscr ma sk all external interrupt requests. a latched interrupt request is not presented to the interrupt prio rity logic unless the corresponding imask bit is clear. note the interrupt mask (i) in the condi tion code register (ccr) masks all interrupt requests, including external interrupt requests. (see figure 11-3 .) 11.3.1 irq1 pin a logic 0 on the irq1 pin can latch an interrupt request into the irq1 latch. a vector fetch, software clear, or reset clears the irq1 latch. if the mode1 bit is set, the irq1 pin is both falling-edge-sensitive and low-level-sensitive. with mode1 set, both of these actions must occur to clear the irq1 latch: vector fetch, software clear, or reset ? a vect or fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interru pt acknowledge signal by writing a logic 1 to the ack1 bit in the interrupt status and contro l register (iscr). the ack1 bit is useful in applications that poll the irq1 pin and require software to clear the irq1 latch. writing to the ack1 bit can also prevent spurious interrupts due to noise. setting ack1 does not affect subsequent transitions on the irq1 pin. a falling edge that occurs after writing to the ack1 bit latches another interrupt request. if the irq1 mask bit, imask1, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq1 pin to logic 1 ? as long as the irq1 pin is at logic 0, the irq1 latch remains set. the vector fetch or software clear and the return of the irq1 pin to logic 1 may occur in any order. the interrupt request remains pending as long as the irq1 pin is at logic 0. if the mode1 bit is clear, the irq1 pin is falling-edge-sensitive only. with mode1 clear, a vector fetch or software clear immediately clears the irq1 latch. use the bih or bil instruction to read the logic level on the irq1 pin. note when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. external interrupt module (irq) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 116 freescale semiconductor figure 11-3. irq interrupt flowchart 11.3.2 irq2 pin when the irq2dis bit is clear, a logic 0 on the irq2 pin can latch an interrupt request into the irq2/keyboard interrupt latch. a vector fetch, software clear, or reset clears the irq2/keyboard interrupt latch. if the mode2 bit is set, the irq2 pin is both falling-edge-sensitive and low-level-sensitive. with mode2 set, both of these actions must occu r to clear the irq2 interrupt latch: from reset i bit set? fetch next yes no interrupt? instruction swi instruction? rti instruction? no stack cpu registers no set i bit load pc with interrupt vector no yes unstack cpu registers execute instruction yes yes irq module during break interrupts mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 117 vector fetch, software clear, or reset ? a vect or fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interru pt acknowledge signal by writing a logic 1 to the ack2 bit in the interrupt status and contro l register (iscr). the ack2 bit is useful in applications that poll the irq2 pin and require software to clear the irq2 interrupt latch. writing to the ack2 bit can also prevent spurious interrupts due to noise. setting ack2 does not affect subsequent transitions on the irq2 pin. a falling edge that occurs after writing to the ack2 bit latches another interrupt request. if the irq2 mask bit, imask2, is cl ear, the cpu loads the program counter with the vector address at locations $ffd2 and $ffd3. return of the irq2 pin to logic 1 ? as long as the irq2 pin is at logic 0, the irq2 interrupt latch remains set. the vector fetch or software clear and the return of the irq2 pin to logic 1 may occur in any order. the interrupt request remains pending as long as the irq2 pin is at logic 0. if the mode2 bit is clear, the irq2 pin is falling-edge-sensitive only. with mode2 clear, a vector fetch or software clear immediately clears the irq2 interrupt latch. to determine the logic level on the irq2 pin, read the irq2 pin state bit, pin2, in the iscr. this bit reflects the value of the irq2 pin, even when the irq2dis bit is set. note see chapter 19 keyboard interrupt (kbi) module for more information about keyboard interrupt. 11.4 irq module du ring break interrupts the system integration module (sim ) controls whether the irq1 and irq2 interrupt latches can be cleared during the break state. the bcfe bit in t he sim break flag control register (sbfcr) enables software to clear the latches during the break state. (see 6.7.3 sim break flag control register .) to allow software to clear the irq1 latch and the irq2 interrupt latch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latches during the break state, write a logic 0 to the bcfe bit. wi th bcfe at logic 0 (its default state), writing to the ack1 and ack2 bits in the irq status and control register during the break state has no effect on the irq latches. see 11.5 irq status and control register . 11.5 irq status and control register the irq status and control register (iscr) controls and monitors operation of the irq module. it has these functions: shows current state of irq2 pin clears the irq1 and irq2 interrupt latches masks irq1 and irq2 interrupt requests controls triggering sensitivity of the irq1 and irq2 interrupt pins disables irq2 interrupt requests external interrupt module (irq) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 118 freescale semiconductor pin2 ? irq2 pin state bit this read-only bit reflects the current logic level of the irq2 pin. 1 = irq2 pin at logic 1 0 = irq2 pin at logic 0 ack2 ? irq2 interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq2/keyboard interrupt latch. ack2 always reads as logic 0. reset clears ack2. imask2 ? irq2 interrupt mask bit writing a logic 1 to this read/write bit prevents the output of the irq2/keyboard interrupt latch from generating interrupt requests. reset clears imask2. 1 = irq2 pin interrupt request disabled 0 = irq2 pin interrupt request enabled mode2 ? irq2/keyboard interrupt edge/level select bit this read/write bit controls the triggering sensitivity of the irq2 interrupt pin. reset clears mode2. 1 = irq2 interrupt request on falling edges and low levels 0 = irq2 interrupt request on falling edges only irq2dis ? irq2 pin interrupt latch disable bit this read/write bit prevents the irq2 pin from latching interrupt requests into the irq2 interrupt latch. reset clears irq2dis. 1 = irq2 pin interrupt requests not latched 0 = irq2 pin interrupt requests latched ack1 ? irq1 interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq1 latch. ack1 always reads as logic 0. reset clears ack1. imask1 ? irq1 interrupt mask bit writing a logic 1 to this read/write bit disables irq1 interrupt requests. reset clears imask1. 1 = irq1 interrupt requests disabled 0 = irq1 interrupt requests enabled mode1 ? irq1 edge/level select bit this read/write bit controls the triggering sensitivity of the irq1 pin. reset clears mode1. 1 = irq1 interrupt request on falling edges and low levels 0 = irq1 interrupt request on falling edges only address: $001d bit 7654321bit 0 read: pin2 0 imask2 mode2 irq2dis 0 imask1 mode1 write: ack2 ack1 reset:00000000 = unimplemented figure 11-4. irq status and control register (iscr) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 119 chapter 12 infrared serial communi cations interface (irsci) 12.1 introduction this section describes the infrared serial comm unications interface (irsci) module which allows high-speed asynchronous communications wi th peripheral devices and other mcus. note references to dma (direc t memory access) and associated functions are only valid if the mcu has a dma module. this mcu does not have the dma function. any dma-related register bits should be left in their reset state for normal mcu operation. 12.2 features features of the irsci module include: full duplex operation software selectable infrared modulation/demodulation (3/16, 1/16, or 1/32) standard mark/space non-retu rn-to-zero (nrz) format programmable 8-bit or 9-bit character length separately enabled transmitter and receiver separate receiver and transmitter cpu interrupt requests two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framing error detection hardware parity checking 1/16 bit-time noise detection infrared serial communi cations interface (irsci) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 120 freescale semiconductor 12.3 irsci module overview the irsci consists of a modified serial communi cations interface (sci) and the infrared interface submodule as shown in figure 12-1 . the infrared block receives two clock sources from the sci, sci_r16xclk and sci_r32xclk, which are configured to generate the narrow pulse width during transmission. the sci_r16xclk and sci_r32xclk are internal clocks with frequencies 16 and 32 times the baud rate, respectively. both sci_r16xclk and sci_r32xclk clocks are used for transmitting data. the sci_r16xclk clock is used only for receiving data. the infrared submodule consists of two major bloc ks: the transmit encoder and the receive decoder which will be discussed in 12.4 infrared functional description . the sci transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow low pulse for every zero bit. no low pulse is transmitted for every one bit. when receiving data, the ir pulses should be detected using an ir photo diode and transformed to cmos levels by the ir re ceive decoder (external from the mcu). the zero pulses are then stretched by the infrared submodule to return to a serial bit stream to be received by the sci. figure 12-1. sci and ir system block diagram caution for proper sci function (transmit or receive), the bus clock (cgmout 2) must be programmed to at least 32 times that of the selected baud rate. note when the infrared submodule is disabled, pins txd and rxd pass through unchanged to the sci. rxd txd txd rxd infrared submodule txd rxd sci_r16xclk sci_r32xclk serial communications cgmout 2 mcu adx/data/control bus tx/rx clock generator interface (sci) infrared functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 121 12.4 infrared functional description the infrared submodule consists of two major blocks : a transmit encoder and a receive decoder as shown in figure 12-2 . figure 12-2. infrared submodule diagram this module provides the capability of transmitting narrow pulses to the ir led and receiving narrow pulses and transforming them to serial bits, which are sent to the sci. the infrared submodule receives its clock sources from the sci. one of these two clo cks are selected in the infrared submodule to generate either 3/16, 1/16, or 1/32 narrow pulses during transmission. 12.4.1 infrared transmit encoder the infrared transmit block converts serial bits of data from the sci module to narrow low pulses (pin txd) when a zero bit in the serial stream is received. th e narrow pulse is sent in the middle of the bit with a duration of 1/32, 1/16, or 3/16 of a bit time . when two 0s are sent, the first narrow pulse is sent in the middle of the bit, and then after one bit time, another narrow pulse is sent in the middle of the second bit. 12.4.2 infrared receive decoder the infrared receive block converts low narrow pulses from pin rxd to standard sci data bits using the sci_r16xck clock. this signal clocks a 4-bit inter nal counter which ranges from 0 to 15. the incoming pulse enables the internal counter and a 0 is sent out to the ir_rxd output. if a second pulse or several pulses occur between count 0 and 7, these pulses ar e ignored. when the counter is greater than 7, and if another pulse occurs, the counter is reset and the ir_rxd output remains 0. after the counter reaches 15, the ir_rxd output returns to 1. the circuit then waits for another input pulse and the process is repeated. if a pulse arrives shortly after the counter reaches 15 due to jitter, the ir_rxd output remains 1 until the pulse occurs. then a 0 is sent out to ir_rxd. rxd txd txd rxd transmit ir_txd rxd sci_r16xclk sci_r32xclk tnp[1:0] mux txd encoder iren receive decoder iren mux ir_rxd infrared serial communi cations interface (irsci) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 122 freescale semiconductor 12.5 sci functional description these changes are made to the standard sci which is used in mc68hc(9)08lj60: the prescaler is eliminated (i ncluding the divide-by-4 stage) to minimize the input frequency and allow for the 32x clock needed for ir modulation. the txinv bit is removed from scc1. the pin control logic was changed to allow for seperate enable/disable of the rxd and/or txd pads based upon whether the associated function is enabled. the clock input to the baud rate generator is not divided by 4. for example, the baud rate equation is different by a factor of 4. figure 12-4 shows the structure of the sci. the sci allows full-duplex, asynchronous, nrz serial communication between the mcu and remote devices , including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. addr. register name bit 7 6 5 4 3 2 1 bit 0 $0013 sci control register 1 (scc1) read: loops ensci 0 m wake ilty pen pty write: reset: 0 0 0 0 0 0 0 0 $0014 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $0015 sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset: u u 0 0 0 0 0 0 $0016 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset: 1 1 0 0 0 0 0 0 $0017 sci status register 2 (scs2) read: bkf rpf write: reset: 0 0 0 0 0 0 0 0 $0018 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) read: 0 0 0 0 0 scr2 scr1 scr0 write: reset: 0 0 0 0 0 0 0 0 $001e sci infrared control register (scircr) read: 0 0 0 0 0 tnp1 tnp0 iren write: reset: 0 0 0 0 0 0 0 0 = unimplemented u = undetermined figure 12-3. irsci i/o register summary sci functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 123 figure 12-4. sci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 dmate orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register dma interrupt control transmitter interrupt control receiver interrupt control error interrupt control control dmare ensci loops ensci rxd txd internal bus txinv loops 16 pre- scaler baud rate generator cgmout 2 infrared serial communi cations interface (irsci) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 124 freescale semiconductor 12.5.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 12-5 . figure 12-5. sci data formats (8-bit/9-bit for standard sci and infrared) 12.5.2 transmitter figure 12-6 shows the structure of the sci transmitter. note the transmission output pin is enabled by te bit of scc2 instead of ensci bit of scc1. 12.5.2.1 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when transmitti ng 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bit (bit 8). 12.5.2.2 character transmission during an sci transmission, the transmit shift register sh ifts a character out to the txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. to initiate an sci transmission: 1. enable the sci by writing a logic 1 to the enable sci bit (ensci) in sci control register 1 (scc1). 2. enable the transmitter by writing a logic 1 to t he transmitter enable bit (te) in sci control register 2 (scc2). 3. clear the sci transmitter empty bit by first reading sci status register 1 (scs1) and then writing to the scdr. 4. repeat step 3 for each subsequent transmission. bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format bit m in scc1 clear start bit bit 0 next stop bit start bit 9-bit data format bit m in scc1 set bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 possible parity bit possible parity bit standard sci data infrared sci data standard sci data infrared sci data sci functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 125 at the start of a transmission, transmitter control logi c automatically loads the tran smit shift register with a preamble of logic 1s. after the preamble shifts ou t, control logic transfers the scdr data into the transmit shift register. a logic 0 start bit automatically goes into the least significant bit (lsb) position of the transmit shift register. a logi c 1 stop bit goes into the most significant bit (msb) position. the sci transmitter empty bit, scte, in scs1 beco mes set when the scdr transfers a byte to the transmit shift register. the scte bi t indicates that the scdr can accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter interrupt request. when the transmit shift register is not transmitting a character, the txd pin goes to the idle condition, logic 1 (in either standard or infrared modes). if at any time software clears the ensci bit in sci control register 1 (scc1), the transmitter and receiver relinquish control of the sci pins. figure 12-6. sci transmitter dmate scte pen pty h876543210l 11-bit transmit stop start t8 dmate scte sctie tcie sbk tc parity generation msb sci data register load from scdr shift enable preamble (all 1s) break (all 0s) transmitter control logic shift register dmate tc sctie tcie scte transmitter cpu int errupt request transmitter dma service request m ensci loops te txd internal bus scr2 scr1 scr0 baud divider sctie (n/a) cgmout 2 infrared serial communi cations interface (irsci) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 126 freescale semiconductor 12.5.2.3 break characters writing a logic 1 to the send break bit, sbk, in s cc2 loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at logic 1, tran smitter logic cont inuously loads break characters into the transmit shift register. afte r software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recogni tion of the start bit of the next character. the sci recognizes a break character when a start bit is followed by eight or ni ne logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has these effects on sci registers: sets the framing error bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci data register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception-in-progress flag (rpf) bits 12.5.2.4 idle characters an idle character contains all logic 1s and has no st art, stop, or parity bit. idle character length depends on the m bit in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a transmission, the txd pin become s idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. note when queueing an idle character, return the te bit to logic 1 before the stop bit of the current character shifts out to the txd pin. setting te after the stop bit appears on txd causes data previously written to the scdr to be lost. a good time to toggle the te bit is when the scte bit becomes set and just before writing the next byte to the scdr. 12.5.2.5 transmitter interrupts these conditions can generate cpu interrupt requests from the sci transmitter: sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests. sci functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 127 12.5.3 receiver figure 12-7 shows the structure of the sci receiver. figure 12-7. sci receiver block diagram all 1s all 0s m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery dmare scrf or orie nf neie fe feie pe peie dmare scrie scrf ilie idle wakeup logic parity checking msb error cpu interrupt request dma service request (n/a) cpu interrupt request sci data register r8 dmare orie neie feie peie scrie ilie rwu scrf idle or nf fe pe internal bus baud divider 16 scr2 scr1 scr0 scrie dmare cgmout 2 rxd infrared serial communi cations interface (irsci) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 128 freescale semiconductor 12.5.3.1 character length the receiver can accommodate either 8-bit or 9-bit data . the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bi t data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 12.5.3.2 character reception during an sci reception, the receive shift register shi fts characters in from the rxd pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive sh ift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status register 1 (scs1) becomes set, indicating that the received byte can be read. if th e sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request. 12.5.3.3 data sampling the receiver samples the rxd pin at the rt clock rate . the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at the following times (see figure 12-8 ): after every start bit after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an a synchronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 12-8. receiver data sampling rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb rxd sci functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 129 to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 12-1 summarizes the results of the start bit verification samples. if start bit verification is not successful, the rt cl ock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 12-2 summarizes the results of the data bit samples. note the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verification, the noi se flag (nf) is set and the receiver assumes that the bit is a start bit. table 12-1. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 table 12-2. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 infrared serial communi cations interface (irsci) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 130 freescale semiconductor to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 12-3 summarizes the results of the stop bit samples. 12.5.3.4 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. the fe flag is set at the same time that the scrf bit is set. a break character that has no st op bit also sets the fe bit. 12.5.3.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bi t data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within char acters corrects misalignments between transmitter bit times and receiver bit times. table 12-3. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 sci functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 131 slow data tolerance figure 12-9 shows how much a slow received characte r can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 12-9. slow data for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 12-9 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 12-9 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles + 3 rt cycl es = 163 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 ? 154 ------------------------- - 100 4.54% = 170 163 ? 170 ------------------------- - 100 4.12% = infrared serial communi cations interface (irsci) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 132 freescale semiconductor fast data tolerance figure 12-10 shows how much a fast received character can be misaligned wit hout causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but is still there for the stop bit data samples at rt8, rt9, and rt10. figure 12-10. fast data for an 8-bit character, data sampling of the stop bit takes the receiver 9bittimes 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 12-10 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 12-10 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 ? 154 ------------------------- - 100 3.90% = 170 176 ? 170 ------------------------- - 100 3.53% = sci functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 133 12.5.3.6 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bi t in scc1, either of two conditio ns on the rxd pin can bring the receiver out of the standby state: address mark ? an address mark is a logic 1 in the most significant bit position of a received character. when the wake bit is set, an address ma rk wakes the receiver from the standby state by clearing the rwu bit. the address mark also se ts the sci receiver full bit, scrf. software can then compare the character containing the addr ess mark to the user-defined address of the receiver. if they are the same, the receiver re mains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. idle input line condition ? when the wake bit is clear, an idle character on the rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. note clearing the wake bit after the rxd pin has been idle may cause the receiver to wake up immediately. 12.5.3.7 receiver interrupts these sources can generate cpu interrupt requests from the sci receiver: sci receiver full (scrf) ? the scrf bit in scs1 indicates that the receive shift register has transferred a character to the s cdr. scrf can generate a receiver interrupt request. setting the sci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. idle input (idle) ? the idle bit in scs1 indicates that 10 or 11 consecutive logic 1s shifted in from the rxd pin. the idle line interrupt enable bi t, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. 12.5.3.8 error interrupts these receiver error flags in scs1 can generate cpu interrupt requests: receiver overrun (or) ? the or bit indicates t hat the receive shift register shifted in a new character before the previous c haracter was read from the scdr. the previous character remains in the scdr, and the new character is lost. th e overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. noise flag (nf) ? the nf bit is set when t he sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate sci error cpu interrupt requests. framing error (fe) ? the fe bit in scs1 is se t when a logic 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. infrared serial communi cations interface (irsci) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 134 freescale semiconductor parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in s cc3 enables pe to generate sci error cpu interrupt requests. 12.6 wait mode the sci module remains active after the execution of a wait instruction. in wait mode the sci module registers are not accessible by the cpu. any enabl ed cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. 12.7 sci during br eak module interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during interrupts generated by the break module. the bcfe bi t in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. to allow software to clear status bits during a break in terrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it rema ins cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o register s during the break state without affecting status bits. some status bits have a two-step read/write clearin g procedure. if software does the first step on such a bit before the break, the bit cannot change during the brea k state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 12.8 i/o signals the two irsci input/output (i/o) pins are: txd ? transmit data rxd ? receive data 12.8.1 txd (transmit data) this pin transmits sci (standard or infrared) data. it will idle high in either mode and is high impedance anytime the transmi tter is disabled. 12.8.2 rxd (receive data) this pin receives sci (standard or infrared) data. an idle line is detected as a line high. this input is ignored when the receiver is disabled and should be terminated to a known voltage. a summary of the i/o pin c onsiderations is given in table 12-4 . i/o registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 135 12.9 i/o registers these i/o registers control and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr) sci infrared control register (scircr) 12.9.1 sci cont rol register 1 sci control register 1: enables loop mode operation enables the sci controls output polarity controls character length controls sci wakeup method controls idle character detection enables parity function controls parity type table 12-4. sci standard and infrared pin functions scircr [iren] sccr1 [ensci] sccr2 [te] sccr2 [re] txd pin rxd pin 0 1 0 0 *hi-z input ignored, terminate externally 0 1 0 1 *hi-z input sampled, pin should idle high 0110 output sci, idle high input ignored, terminate externally 0111 output sci, idle high input sampled, pin should idle high 1 1 0 0 *hi-z input ignored, terminate externally 1 1 0 1 *hi-z input sampled, pin should idle high 1110 output ir, idle high input ignored, terminate externally 1111 output ir, idle high input sampled, pin should idle high x 0 x x hi-z input ignored, terminate externally * after completion of transmission in progress infrared serial communi cations interface (irsci) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 136 freescale semiconductor loops ? loop mode select bit this bit enables loop mode operation for the sci onl y. in loop mode the rxd pin is disconnected from the sci, and the transmitter output goes into the rece iver input. both the trans mitter and the receiver must be enabled to use loop mode. this bit does not affect the infrared encoder/decoder. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this bit enables the sci and the sci baud rate generator. clearing ensci sets the scte and tc bits in sci status register 1 and disables transmitter interrupts. 1 = sci enabled 0 = sci disabled m ? mode (character length) bit this bit determines whether sci characte rs are eight or nine bits long. (see table 12-5 .) the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup condition bit this bit determines which condition wakes up the sci: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the rxd pin. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this bit determines when the sci starts counting l ogic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if th e count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition , but requires properly synchronized transmissions. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit pen ? parity enable bit this bit enables the sci parity function. (see table 12-5 .) when enabled, the parity function inserts a parity bit in the most significant bit position. (see figure 12-5 .) 1 = parity function enabled 0 = parity function disabled address: $0013 bit 7654321bit 0 read: loops ensci 0 m wake ilty pen pty write: reset:00000000 figure 12-11. sci control register 1 (scc1) i/o registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 137 pty ? parity bit this bit determines whether the sci generates and checks for odd parity or even parity. (see table 12-5 .) 1 = odd parity 0 = even parity note changing the pty bit in the middle of a transmission or reception can generate a parity error. 12.9.2 sci cont rol register 2 sci control register 2: enables the following cpu interrupt requests: ? enables the scte bit to generate transmitter interrupt requests ? enables the tc bit to generate transmitter interrupt requests ? enables the scrf bit to generate receiver interrupt requests ? enables the idle bit to generate receiver cpu interrupt requests enables the transmitter enables the receiver enables sci wakeup transmits sci break characters table 12-5. character format selection control bits character format m pen:pty start bits data bits parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 0 10 1 7 even 1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8 even 1 11 bits 1 11 1 8 odd 1 11 bits address: $0014 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 12-12. sci control register 2 (scc2) infrared serial communi cations interface (irsci) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 138 freescale semiconductor sctie ? sci transmit interrupt enable bit this bit enables the scte bit to generate sci transmitter interrupt requests. setting the sctie bit and clearing the dma transfer enable bit, dmate, in scc3 enables the scte bit to generate cpu interrupt requests. 1 = scte enabled to generate cpu interrupt if dmate is cleared 0 = scte not enabled to generate interrupt requests tcie ? transmission complete interrupt enable bit this bit enables the tc bit to generate sci transmitter cpu interrupt requests. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? sci receive interrupt enable bit this read/write bit enables the scrf bit to generate sci receiver cpu interrupt requests or sci receiver dma service requests. setting the scri e bit and clearing the dma receive enable bit, dmare, in scc3 enables the scrf bit to generate cpu interrupt requests. 1 = scrf enabled to generate interrupt requests if dmate is cleared 0 = scrf not enabled to generate interrupt requests ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to generate sci receiver cpu interrupt requests. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests te ? transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the txd pin. if softw are clears the te bit, the transmitter completes any transmission in progress before the txd returns to the high impedence state. clearing and then setting te during a transmission queues an id le character to be sent after the character currently being transmitted. 1 = transmitter enabled 0 = transmitter disabled note writing to the te bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. re ? receiver enable bit setting this bit enables the receiver. clearing the re bit disables the receiver but does not affect receiver interrupt flag bits. 1 = receiver enabled 0 = receiver disabled note writing to the re bit is not allowe d when the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wakeup bit this bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the rwu bit. 1 = standby state 0 = normal operation i/o registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 139 sbk ? send break bit setting and then clearing this read/write bit transmi ts a break character followed by a logic 1. the logic 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmi ts break characters with no logic 1s between them. 1 = transmit break characters 0 = no break characters being transmitted note do not toggle the sbk bit immediately a fter setting the scte bit. toggling sbk too early causes the sci to send a break character instead of a preamble. 12.9.3 sci cont rol register 3 sci control register 3: stores the ninth sci data bit received and the ninth sci data bit to be transmitted enables these interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts ? parity error interrupts r8 ? received bit 8 when the sci is receiving 9-bit characters, r8 is the re ad-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other eight bits. when the sci is receiving 8-bit characters, r8 is a copy of the eighth bit (bit 7). t8 ? transmitted bit 8 when the sci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift regi ster at the same time that the scdr is loaded into the transmit shift register. dmare ? dma receive enable bit this bit enables the dma to service sci receiver dma service requests generated by the scrf bit. (see 12.9.4 sci status register 1 .) setting the dmare bit disables sci receiver cpu interrupt requests. 1 = dma enabled to service sci receiver dma service requests generated by the scrf bit (sci receiver cpu interrupt requests disabled) 0 = dma not enabled to service sci receiver dma service requests generated by the scrf bit (sci receiver cpu interrupt requests enabled) caution there is no dma on this device. this bit should be cleared. address: $0015 bit 7654321bit 0 read: r8 t8 dmare dmate orie neie feie peie write: reset:uu000000 = unimplemented u = unaffected figure 12-13. sci control register 3 (scc3) infrared serial communi cations interface (irsci) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 140 freescale semiconductor dmate ? dma transfer enable bit this bit enables sci transmitter em pty (scte) dma service requests. (see 12.9.4 sci status register 1 .) setting the dmate bit disables scte cpu interrupt requests. 1 = scte dma service requests enabled (sct e cpu interrupt requests disabled) 0 = scte dma service requests disabled (scte cpu interrupt requests enabled) caution there is no dma on this device. this bit should be cleared. orie ? receiver overrun interrupt enable bit this bit enables sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt requests from or bit enabled 0 = sci error cpu interrupt r equests from or bit disabled neie ? receiver noise error interrupt enable bit this bit enables sci error cpu interrupt requests generated by the noise error bit, ne. 1 = sci error cpu interrupt requests from ne bit enabled 0 = sci error cpu interrupt requests from ne bit disabled feie ? receiver framing error interrupt enable bit this bit enables sci error cpu interrupt requests generated by the framing error bit, fe. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt requests from fe bit disabled peie ? receiver parity error interrupt enable bit this bit enables sci receiver cpu interrupt requests generated by the parity error bit, pe. (see 12.9.4 sci status register 1 .) 1 = sci error cpu interrupt requests from pe bit enabled 0 = sci error cpu interrupt requests from pe bit disabled 12.9.4 sci status register 1 sci status register 1 contains flags to signal these conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift register data to scdr complete receiver input idle receiver overrun noisy data framing error parity error address: $0016 bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 12-14. sci status register 1 (scs1) i/o registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 141 scte ? sci transmitter empty bit this clearable, read-only bit is set when the scdr tr ansfers a character to the transmit shift register. scte can generate an sci transmitter interrupt request. when the sctie bit in scc2 is set and the dmate bit in scc3 is clear, scte generates an sci transmitter cpu interrupt request. clear the scte bit by reading scs1 with scte set and then writing to scdr. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register tc ? transmission complete bit this read-only bit is set when the scte bit is se t, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is automatically cleared when data, preamble, or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency be tween queueing data, preamble, and break and the transmission actually starting. 1 = no transmission in progress 0 = transmission in progress scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf can generate an sci receiver interrupt request. when the scrie bit in scc2 is set and the dmare bit in scc3 is clear, scrf generates a cpu interrupt request. clear the scrf bit by reading scs1 with scrf set and then reading the scdr. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an sci error cpu interrupt request if the ilie bit in scc2 is also set and the dmare bit in scc3 is clear. clear the idle bit by read ing scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit before an idle condition can set the idle bit. al so, after the idle bit has been cl eared, a valid character must again set the scrf bit before an idle condition can set the idle bit. 1 = receiver input idle 0 = receiver input active (or id le since the idle bit was cleared) or ? receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an sci error cpu interrupt request if the orie bit in scc3 is also set. the da ta in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an ove rrun to occur between reads of sc s1 and scdr in the flag-clearing sequence. figure 12-15 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearin g sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-clearing sequence reads byte 3 in the scdr instead of byte 2. in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. infrared serial communi cations interface (irsci) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 142 freescale semiconductor nf ? receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is al so set. clear the nf bit by reading scs1 and then reading the scdr. 1 = noise detected 0 = no noise detected figure 12-15. flag clearing sequence fe ? receiver framing error bit this clearable, read-only bit is set when a logic 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. 1 = framing error detected 0 = no framing error detected pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. 1 = parity error detected 0 = no parity error detected byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr (byte 1) scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr (byte 2) scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr (byte 3) scrf = 0 byte 1 read scs1 scrf = 1 read scdr (byte 1) scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr (byte 3) delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 i/o registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 143 12.9.5 sci status register 2 sci status register 2 contains flags to signal the following conditions: break character detected incoming data bkf ? break flag bit this clearable, read-only bit is set when the sci detects a break character on the rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate an interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become set again on ly after logic 1s agai n appear on the rxd pin followed by another break character. 1 = break character detected 0 = no break character detected rpf ?reception-in-progress flag bit this bit is set when the receiver detects a logic 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch, or w hen the receiver detects an idle character. polling rpf before disabling the sci module or entering st op mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress 12.9.6 sci data register the sci data register is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the sci data register. r7/t7?r0/t0 ? receive/transmit data bits reading the scdr accesses the read-only received dat a bits, r7?r0. writing to the scdr writes the data to be transmitted, t7?t0. address: $0017 bit 7654321bit 0 read: bkf rpf write: reset:00000000 = unimplemented figure 12-16. sci status register 2 (scs2) address: $0018 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 12-17. sci data register (scdr) infrared serial communi cations interface (irsci) mc68hc08lk60 ? mc68hc908lk60 advance information data sheet, rev. 1.1 144 freescale semiconductor 12.9.7 sci baud rate register the baud rate register selects the baud rate for both the receiver and the transmitter. scr2?scr0 ? sci baud rate select bits these read/write bits select the sci baud rate divisor as shown in table 12-6 . caution for proper sci function, the bus clock (cgmout 2) must be programmed to at least 32 times that of sci baud rate. use the following formula to calculate the sci baud rate: where: cgmout 2 = bus frequency bd = baud rate divisor address: $0019 bit 7654321bit 0 read:00000 scr2 scr1 scr0 write: reset:00000000 = unimplemented figure 12-18. sci baud rate register (scbr) table 12-6. sci baud rate selection scr2:1:0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate = cgmout 2 16 x bd i/o registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 145 table 12-7 shows the sci baud rates that can be generated with a 307.2-khz input clock. caution do not select 1/32 transmission (tnp1:0 = 11/10) for the highest baud rate (scr2:0 = 000). a 32x clock is not available under these conditions. 12.9.8 sci infrared control register the infrared control register is a read/write register c ontaining the control bits for the infrared submodule. the iren bit has to be set for any of the other bits c an operate. the configuration of this register in reset is shown in figure 12-19 . tnp1 and tnp0 ? transmitter narrow pulse bits these bits enable whether the sci transmit s a 1/16, 3/16, or 1/32 narrow pulse. 11 = sci transmits a 1/32 narrow pulse. 10 = sci transmits a 1/32 narrow pulse. 01 = sci transmits a 1/16 narrow pulse. 00 = sci transmits a 3/16 narrow pulse. iren ? ir enable bit this bit enables the entire infrared submodule. when this bit is clear, the ir is disabled. 1 = ir enabled 0 = ir disabled table 12-7. sci baud rate selection examples scr2:1:0 baud rate divisor (bd) baud rate (cgmout 2 = 307.2 khz) 000 1 19,200 001 2 9600 010 4 4800 011 8 2400 100 16 1200 101 32 600 110 64 300 111 128 150 address: $001e bit 7654321bit 0 read:00000 tnp1 tnp0 iren write: reset:00000000 = unimplemented figure 12-19. sci infrared control register (scircr) infrared serial communi cations interface (irsci) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 146 freescale semiconductor mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 147 chapter 13 serial peripheral interface module (spi) 13.1 introduction this section describes the serial peripheral interfac e (spi) module which allows full-duplex, synchronous, serial communications with peripheral devices. note references to dma and associated f unctions are only valid if the mcu has a dma module. this mcu does not have the dma function. any dma-related register bits should be left in their reset state for normal mcu operation. 13.2 features features of the spi module include: full-duplex operation master and slave modes double-buffered operation with separate transmit and receive registers four master mode frequencies (maximum = bus frequency 2) maximum slave mode frequency = bus frequency clock ground for reduced radio frequency (rf) interference serial clock with programmable polarity and phase two separately enabled interrupts: ? sprf (spi receiver full) ? spte (spi transmitter empty) mode fault error flag with cpu interrupt capability overflow error flag with cpu interrupt capability programmable wired-or mode i 2 c (inter-integrated circuit) compatibility serial peripheral in terface module (spi) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 148 freescale semiconductor 13.3 functional description figure 13-1 shows the locations and contents of the spi input/output (i/o) registers and figure 13-2 shows the structure of the spi module. the spi module allows full-duplex, synchronous, serial communication among the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt-driven. the following paragraphs describe the operation of the spi module. 13.3.1 master mode the spi operates in master mode when the spi master bit, spmstr, is set. note configure the spi modules as master or slave before enabling them. enable the master spi before enabling t he slave spi. disable the slave spi before disabling the master spi. (see 13.13.1 spi control register .) only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the transmit data register. if the sh ift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte. the byte begins shifting out on the mosi pin under the control of the serial clock. (see figure 13-3 .) the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register. (see 13.13.2 spi status and control register .) through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. as the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the master?s miso pin. the transmission ends when the receiver full bit, sprf, becomes set. at the same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. writing to the spi data register clears the spte bit. addr. register name bit 7 6 5 4 3 2 1 bit 0 $000d spi control register (spcr) read: sprie dmas spmstr cpol cpha spwom spe sptie write: reset:00101000 $000e spi status and control register (spscr) read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 $000f spi data register (spdr) read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset = unimplemented figure 13-1. spi i/o register summary functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 149 figure 13-2. spi module block diagram transmitter cpu interrupt request receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 cgmout 2 clock select 2 clock divider 8 32 128 clock logic cpha cpol spi sprie dmas spe spwom sprf spte ovrf m s pin control logic receive data register sptie spe internal bus from sim modfen errie control modf spmstr mosi miso spsck ss serial peripheral in terface module (spi) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 150 freescale semiconductor figure 13-3. full-duplex master-slave connections 13.4 slave mode the spi operates in slave mode when the spmstr bit is clear. in slave mode, the spsck pin is the input for the serial clock from the master mcu. before a data transmission occurs, the ss pin of the slave spi must be at logic 0. ss must remain low until the transmission is complete. (see 13.7.2 mode fault error .) in a slave spi module, data enters the shift register und er the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it transfers to the receive data register, and the sprf bit is set. to prevent an overflow condit ion, slave software then must read the receive data register before another full byte enters the shift register. the maximum frequency of the spsck fo r an spi configured as a slave is the bus clock speed (which is twice as fast as the fastest master spsck clock t hat can be generated). th e frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. the slave must write to its tr ansmit data register at l east one bus cycle before the master starts the next transmission. otherwise, the byte already in the slave shift register shifts out on the miso pin. data written to the slave shift register during a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first e dge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. (see 13.5 transmission formats .) note spsck must be in the proper idle state before the slave is enabled to prevent spsck from appearing as a clock edge. shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss transmission formats mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 151 13.5 transmission formats during an spi transmission, data is simultaneously tr ansmitted (shifted out serially) and received (shifted in serially). a serial clock synchronizes shifting and sampling on the two serial data lines. a slave select line allows selection of an individual slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the slave select line can be optionally used to indicate multiple-master bus contention. 13.5.1 clock phase and polarity controls software can select any of four combinations of se rial clock (spsck) phase a nd polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no signi ficant effect on the transmission format. the clock phase (cpha) control bit selects one of tw o fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with periphera l slaves having different requirements. note before writing to the cpol bit or the cpha bit, disable the spi by clearing the spi enable bit (spe). 13.5.2 transmission format when cpha = 0 figure 13-4 shows an spi transmission in which cpha is logic 0. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slav e. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconf igured as general-purpose i/o not affecting the spi. (see 13.7.2 mode fault error .) when cpha = 0, the first spsck edge is the msb capture strobe. therefore the slave must begin driving its data before th e first spsck edge, and a falling edge on the ss pin is used to start the slave data transmission. the slave?s ss pin must be toggled back to high and then low again between each byte transmitted as shown in figure 13-5 . note the ss pin on this device cannot be configured as a general-purpose i/o. when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the falling edge of ss . any data written after the falling edge is stored in th e transmit data register and transferred to the shift register after the current transmission. serial peripheral in terface module (spi) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 152 freescale semiconductor figure 13-4. transmission format (cpha = 0) figure 13-5. cpha/ss timing 13.5.3 transmission format when cpha = 1 figure 13-6 shows an spi transmission in which cpha is logic 1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slav e. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconf igured as general-purpose i/o not affecting the spi. (see 13.7.2 mode fault error .) when cpha = 1, the master begins driving its mosi pin on the first spsck edge. therefore, the slave uses the first sps ck edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be preferable in systems having only one master and only one slave driving the miso data line. note the ss pin on this device cannot be configured as a general-purpose i/o. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 1234 5678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol = 1 mosi from master miso from slave ss; to slave capture strobe byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1 transmission formats mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 153 figure 13-6. transmission format (cpha = 1) when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the first edge of spsck. any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission. 13.5.4 transmission initiation latency when the spi is configured as a master (spmstr = 1), writing to the spdr st arts a transmission. cpha has no effect on the delay to the start of the transmiss ion, but it does affect the initial state of the spsck signal. when cpha = 0, the spsck signal remains inactive for the first half of the first spsck cycle. when cpha = 1, the first spsck cycl e begins with an edge on the spsck line from its inactive to its active level. the spi clock rate (selected by spr1 :spr0) affects the delay from the write to spdr and the start of the spi transmission. (see figure 13-7 .) the internal spi clock in the master is a free-running derivative of the internal mcu clock. to conserve power, it is enabled only when both the spe and spmstr bits are set. spsck edges occur halfway through the low time of the internal mcu clock. since the spi clock is free-running, it is uncertain where the write to the spdr occurs relative to the slower spsck. this uncertainty caus es the variation in the in itiation delay shown in figure 13-7 . this delay is no longer than a single spi bit time. that is, the maximum delay is two mcu bus cycles for div2, eight mcu bus cycles for div8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 1234 5678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss; to slave capture strobe serial peripheral in terface module (spi) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 154 freescale semiconductor figure 13-7. transmission start delay (master) write to spdr initiation delay bus mosi spsck cpha = 1 spsck cpha = 0 spsck cycle number msb bit 6 12 clock write to spdr earliest latest spsck = internal clock 2; earliest latest 2 possible start points spsck = internal clock 8; 8 possible start points earliest latest spsck = internal clock 32; 32 possible start points earliest latest spsck = internal clock 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock ? ? ? ? ? ? ? ? initiation delay from write spdr to transfer begin queuing transm ission data mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 155 13.6 queuing tr ansmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transm itted immediately after the previous transmission has completed. the spi transmitter empty flag (spte) indicates when the transmit data buffer is ready to accept new data. write to the transmit da ta register only when the spte bit is high. figure 13-8 shows the timing associated wi th doing back-to-back transmissi ons with the spi (spsck has cpha: cpol = 1:0). figure 13-8. sprf/spte cpu interrupt timing the transmit data buffer allows back- to-back transmissions without the sl ave precisely timing its writes between transmissions as in a system with a single data buffer. also, if no new data is written to the data buffer, the last value contained in the shift r egister is the next data word to be transmitted. for an idle master or idle slave that has no data loaded into its transmit buffer, the spte is set again no more than two bus cycles after the transmit buffer emptie s into the shift register. this allows the user to queue up a 16-bit value to send. for an already active sl ave, the load of the shift register cannot occur until the transmission is completed. this implies that a back-to-back write to the transmit data register is not possible. the spte indicates when the next write can occur. bit 3 mosi spsck; cpha:cpol = 1:0 spte write to spdr 1 cpu writes byte 2 to spdr, queueing cpu writes byte 1 to spdr, clearing byte 1 transfers from transmit data 3 1 2 2 3 5 spte bit. register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 byte 2 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. byte 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set. serial peripheral in terface module (spi) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 156 freescale semiconductor 13.7 error conditions these flags signal spi error conditions: overflow (ovrf) ? failing to read the spi data register before the next full byte enters the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read. ovrf is in the spi status and control register. mode fault error (modf) ? the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. modf is in the spi status and control register. 13.7.1 overflow error the overflow flag (ovrf) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of th e next transmission occurs. the bit 1 capture strobe occurs in the middle of spsck cycle 7. (see figure 13-4 and figure 13-6 .) if an overflow occurs, all data received after the overflow and before the ovrf bit is cleared does not transfer to the receive data register and does not set the spi receiver full bit (sprf). the unread data that transferred to the receive data register before the overflow occurred can still be read. therefore, an overflow error always indicates the loss of data. clear the overflow flag by reading the spi status and control register and then reading the spi data register. ovrf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. it is not possible to enable modf or ovrf individually to generate a re ceiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. if the cpu sprf interrupt is enabled and the ovrf in terrupt is not, watch for an overflow condition. figure 13-9 shows how it is possible to mi ss an overflow. the first part of figure 13-9 shows how it is possible to read the spscr and spdr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf bit c an be set in between the time that spscr and spdr are read. figure 13-9. missed read of overflow condition read spdr read spscr ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is not cleared. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. error conditions mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 157 in this case, an overflow can easily be missed. since no more sprf interrupts can be generated until this ovrf is serviced, it is not obvious that bytes are being lost as more transmissions are completed. to prevent this, either enable the ovrf interrupt or do another read of the spscr following the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions can set the sprf bit. figure 13-10 illustrates this process. g enerally, to avoid this second spscr read, enable the ovrf to the cpu by setting the errie bit. figure 13-10. clearing sprf when ovrf interrupt is not enabled 13.7.2 mode fault error setting the spmstr bit selects master mode and configures the spsck and mosi pins as outputs and the miso pin as an input. clearing spmstr sele cts slave mode and configures the spsck and mosi pins as inputs and the miso pin as an output. the mode fault bit, modf, becomes set any time the state of the slave select pin, ss , is inconsistent with the mode selected by spmstr. to prevent spi pin contention and damage to the mcu, a mode fault error occurs if: the ss pin of a slave spi goes high during a transmission. the ss pin of a master spi goes low at any time. for the modf flag to be set, the mode fault error enable bit (modfen) must be set. clearing the modfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. modf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. it is not possible to enable modf or ovrf individually to generate a re ceiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. read spdr read spscr ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. serial peripheral in terface module (spi) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 158 freescale semiconductor in a master spi with the mode fault enable bit (modfe n) set, the mode fault flag (modf) is set if ss goes to logic 0. a mode fault in a master spi causes the following events to occur: if errie = 1, the spi generates an spi receiver/error cpu interrupt request. the spe bit is cleared. the spte bit is set. the spi state counter is cleared. when configured as a slave (spmstr = 0), the modf flag is set if ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends once the incoming spsck goes back to its idle level following the shift of the eighth data bit. when cpha = 1, the transmission begins when the spsck leaves its idle level and ss is already low. the transmi ssion continues until the spsck returns to its idle level following the shift of the last data bit. (see 13.5 transmission formats .) note setting the modf flag does not clear the spmstr bit. the spmstr bit has no function when spe = 0. reading spmstr when modf = 1 shows the difference between a modf occurring when the spi is a master and when it is a slave. note when cpha = 0, a modf occurs if a slave is selected (ss is at logic 0) and later unselected (ss is at logic 1) even if no spsck is sent to that slave. this happens because ss at logic 0 indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then late r unselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), the modf bit generates an spi receiver/error cpu interrupt request if the errie bit is set. the modf bit does not clear the spe bi t or reset the spi in any way. software can abort the spi transmission by clear ing the spe bit of the slave. note a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. to clear the modf flag, read the spscr with the modf bit set and then write to the spcr register. this entire clearing mechanism must occur with no modf condition existing or else the flag is not cleared. 13.8 interrupts the four spi status flags that can be enabled to generate cpu interrupt requests are discussed in table 13-1 . reading the spi status and control register with sprf set and then reading the receive data register clears sprf. the clearing mechanism for the spte flag is always just a write to the transmit data register. the spi transmitter interrupt enable bit (sptie) enabl es the spte flag to generate transmitter interrupt requests provided that the spi is enabled (spe = 1). interrupts mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 159 the spi receiver interrupt enable bit (sprie) enables the sprf bit to generate receiver interrupt requests regardless of the state of the spe bit. (see figure 13-11 .) the error interrupt enable bit (errie) enables both the modf and ovrf bits to generate a receiver/error cpu interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf bit is enabled by the errie bit to generate receiver/error cpu interrupt requests. figure 13-11. spi interrupt request generation these sources in the spi status and control register can generate interrupt requests: spi receiver full bit (sprf) ? the sprf bit becomes set every time a byte transfers from the shift register to the receive data register. if the spi receiver interrupt enable bit, sprie, is also set, sprf generates an spi receiver/error cpu interrupt request. spi transmitter empty (spte) ? the spte bit becom es set every time a by te transfers from the transmit data register to the shift register. if the spi transmit interrupt enable bit, sptie, is also set, spte generates an spte cpu interrupt request or an spte dma service request. table 13-1. spi interrupts flag request spte transmitter empty spi transmitter cpu interrupt request (dmas = 0, sptie = 1, spe = 1) sprf receiver full spi receiver cpu interrupt request (dmas = 0, sprie = 1) ovrf overflow spi receiver/error interrupt request (errie = 1) modf mode fault spi receiver/error interrupt request (errie = 1) not available spte sptie sprf sprie dmas errie modf ovrf spe spi transmitter cpu interrupt request not available spi receiver/error cpu interrupt request serial peripheral in terface module (spi) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 160 freescale semiconductor 13.9 resetting the spi any system reset completely resets the spi. partia l resets occur whenever th e spi enable bit (spe) is low. whenever spe is low, the following occurs: the spte flag is set. any transmission currently in progress is aborted. the shift register is cleared. the spi state counter is cleared, making it ready for a new complete transmission. these items are reset only by a system reset: all control bits in the spcr register all control bits in the spscr regist er (modfen, errie, spr1, and spr0) the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe betw een transmissions without having to set all control bits again when spe is set back high for t he next transmission. by not resetting the sprf, ovrf, and modf flags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing 0 to the spe bit. the spi can also be disabled by a mode fault occurring in an spi that wa s configured as a master with the modfen bit set. 13.10 wait mode the spi module remains active after the execution of a wait instruction. in wait mode, the spi module registers are not accessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. 13.11 spi during break interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see 6.7.3 sim break flag control register .) to allow software to clear status bits during a break in terrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it rema ins cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o register s during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. since the spte bit cannot be cleared during a break wi th the bcfe bit cleared, a write to the transmit data register in break mode does not initiate a transm ission nor is this data transferred into the shift register. therefore, a write to the spdr in br eak mode with the bcfe bit cleared has no effect. i/o signals mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 161 13.12 i/o signals the spi module has five dedicated i/o pins. miso ? data received mosi ? data transmitted spsck ? serial clock ss ? slave select ev ss ? clock ground the spi has limited inter-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becom es an open-drain output when the spwom bit in the spi control register is set. in i 2 c communication, the mosi and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd . 13.12.1 master in/slave out (miso) miso is one of the two spi module pins that transmits serial data. in full- duplex operation, the miso pin of the master spi module is connected to the miso pin of the slave spi module. the master spi simultaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enabled only w hen the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is logic 0 and its ss pin is at logic 0. to support a multiple-slave system, a logic 1 on the ss pin puts the miso pin in a high-impedance state. when enabled, the spi controls data direction of the mi so pin regardless of the st ate of the data direction register of the shared i/o port. note the miso pin on this device is not shared with an i/o port. 13.12.2 master ou t/slave in (mosi) mosi is one of the two spi module pins that transmits se rial data. in full duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. when enabled, the spi controls data direction of the mo si pin regardless of the st ate of the data direction register of the shared i/o port. note the mosi pin on this device is not shared with an i/o port. 13.12.3 serial clock (spsck) the serial clock synchronizes data transmission between master and sl ave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the cl ock input. in full-duplex operation, the master and slave mcus exchange a byte of data in eight serial clock cycles. when enabled, the spi contro ls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port. note the spsck pin on this device is not shared with an i/o port. serial peripheral in terface module (spi) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 162 freescale semiconductor 13.12.4 slave select (ss ) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. (see 13.5 transmission formats .) since it is used to indicate the start of a transmission, the ss must be toggled high and low between each byte transmitted for the cpha = 0 format. however, it can remain low between transmissions for the cpha = 1 format. see figure 13-12 . figure 13-12. cpha/ss timing when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general -purpose i/o regardless of the state of th e modfen control bit. however, the modfen bit can still prevent the state of the ss from creating a modf error. (see 13.13.2 spi status and control register .) note a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high-impedance state. the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. when an spi is configured as a master, the ss input can be used in conjunc tion with the modf flag to prevent multiple masters from driving mosi and spsck. (see 13.7.2 mode fault error .) for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is low for an spi master, the ss pin can be used as a general-purpose i/o under the control of the data direction register of the shared i/o port. with modfen high, it is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. note the ss pin on this device cannot be used as a general-purpose i/o. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and reading the port data register. (see table 13-2 .) 13.12.5 clock ground (ev ss ) ev ss is the ground return for the se rial clock pin, spsck, and the gr ound for the port output buffers. table 13-2. spi configuration spe spmstr modfen spi configuration state of ss logic 0 x (1) 1. x = don?t care x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1 i/o registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 163 13.13 i/o registers three registers control and monitor spi operation: spi control register (spcr) spi status and control register (spscr) spi data register (spdr) 13.13.1 spi control register the spi control register: enables spi module interrupt requests selects cpu interrupt requests configures the spi module as master or slave selects serial clock polarity and phase configures the spsck, mosi, and miso pins as open-drain outputs enables the spi module sprie ? spi receiver interrupt enable bit this read/write bit enables interrupt requests generated by the sprf bit. the sprf bit is set when a byte transfers from the shift register to the receive data register. 1 = sprf cpu interrupt requests or sprf dma service requests enabled 0 = sprf cpu interrupt requests or sprf dma service requests disabled dmas ?dma select bit this read/write bit has no effect on this version of the spi. this bit always read as 0. 0 = spre dma and spte dma service requests disabled spmstr ? spi master bit this read/write bit selects master mode operation or slave mode operation. 1 = master mode 0 = slave mode cpol ? clock polarity bit this read/write bit determines the logic stat e of the spsck pin betw een transmissions. (see figure 13-4 and figure 13-6 .) to transmit data between spi modules, the spi modules must have identical cpol values. cpha ? clock phase bit this read/write bit controls the timing relati onship between the serial clock and spi data. (see figure 13-4 and figure 13-6 .) to transmit data between spi modules, the spi modules must have identical cpha values. when cpha = 0, the ss pin of the slave spi module must be set to logic 1 between bytes. (see figure 13-12 .) address: $000d bit 7654321bit 0 read: sprie dmas spmstr cpol cpha spwom spe sptie write: reset:00101000 figure 13-13. spi control register (spcr) serial peripheral in terface module (spi) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 164 freescale semiconductor spwom ? spi wired-or mode bit this read/write bit disables the pullup devices on pins spsck, mos i, and miso pins so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull spsc k, mosi, and miso pins spe ? spi enable bit this read/write bit enables the spi module. cleari ng spe causes a partial reset of the spi. (see 13.9 resetting the spi .) 1 = spi module enabled 0 = spi module disabled sptie? spi transmit interrupt enable bit this read/write bit enables interrupt requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. 1 = spte interrupt requests enabled 0 = spte interrupt requests disabled 13.13.2 spi status and control register the spi status and control register c ontains flags to si gnal these conditions: receive data register full failure to clear sprf bit before next byte is received (overflow error) inconsistent logic level on ss pin (mode fault error) transmit data register empty the spi status and control register also c ontains bits that perform these functions: enable error interrupts enable mode fault error detection select master spi baud rate sprf ? spi receiver full bit this clearable, read-only flag is set each time a byte tr ansfers from the shift register to the receive data register. sprf generates an interrupt request if the sprie bit in the spi control register is set also. 1 = receive data register full 0 = receive data register not full errie ? error interrupt enable bit this read/write bit enables the modf and ovrf bits to generate cpu interrupt requests. reset clears the errie bit. 1 = modf and ovrf can generate cpu interrupt requests. 0 = modf and ovrf cannot generate cpu interrupt requests. address: $000e bit 7654321bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 = unimplemented figure 13-14. spi status and control register (spscr) i/o registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 165 ovrf ? overflow bit this clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. in an ov erflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the receive data register. 1 = overflow 0 = no overflow modf ? mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission with the modfen bit set. in a master spi, the modf flag is set if the ss pin goes low at any time with the modfen bit set. clear the modf bit by reading t he spi status and control register (spscr) with modf set and then writing to the spi control register (spcr). 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte ? spi transmitter empty bit this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an interrupt request if the sptie bit in the spi control register is set also. 1 = transmit data register empty 0 = transmit data register not empty note do not write to the spi data register unless the spte bit is high. modfen ? mode fault enable bit this read/write bit, when set to 1, allows the modf flag to be set. if the modf flag is set, clearing the modfen does not clear the modf flag. if the modfen bit is low, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. (see 13.7.2 mode fault error .) spr1 and spr0 ? spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 13-3 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use this formula to calculate the spi baud rate: cgmout = base clock output of the clock generator module (cgm) bd = baud rate divisor table 13-3. spi master baud rate selection spr1 and spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 baud rate cgmout 2bd -------------------------- = serial peripheral in terface module (spi) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 166 freescale semiconductor 13.13.3 spi data register the spi data register consists of the read-only receive data register and the write-only transmit data register. writing to the spi data register writes dat a into the transmit data register. reading the spi data register reads data from the receive data register. the transmit data and receive data registers are separate registers that can c ontain different values. (see figure 13-2 .) r7?r0/t7?t0 ? receive/transmit data bits note do not use read-modify-write instructio ns on the spi data register since the register read is not the same as the register written. address: $000f bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset figure 13-15. spi data register (spdr) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 167 chapter 14 alert output generator (alr) 14.1 introduction this section describes the alert output generaor (a lr), which provides 14 software selectable square wave output frequencies. 14.2 features features of the alr module include: 14 software selectable audio alert tone outputs 4-bit software selectable sound pressure level control 14.3 functional description this system will be used to generate alert tones as the output signal alert. the audio alert tone generator is controlled by the four control bits as shown in table 14-1 . this allows 14 possible frequencies to drive the alert output. the zero state acts as an off mode and places the output in a high-impedance mode and an on mode places the output in ground state. note the alert module is enabled only when the on-chip phase locked loop (pll) is engaged. during wait mode, the alcr register should be programmed with value $00 to ensure a three- state output and eliminate any residual output from the audio frequency generator. table 14-1. audio alert tone generator divider ratios al3?al0 audio alert generator fr equencies at given f osc f osc 32.768 khz 32.000 khz 38.4 khz 0000 off hi-z hi-z hi-z 0001 f osc 32 1024 10001 1200 0010 f osc 8 4096 4000 4800 0011 f osc 16 2048 2000 2400 0100 f osc 6 5461 5333 6400 0101 f osc 12 2730 2666 3200 0110 f osc 24 1365 1333 1600 0111 f osc 48 683 667 800 continued on next page alert output generator (alr) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 168 freescale semiconductor 14.3.1 alert control register the alert control register (alcr) bits are in figure 14-1 . al3?al0 ? alert frequency select bits the value of these bits determines the frequency of the alert output (see table 14-1 ). if these bits are set to all 0s, the alert output will be high impedanc e (off). if set to all 1s, the alert output will be at v ss (logic 0). reset clears these bits, turning this output off to the high-impedance state. 14.3.2 sound press ure level circuit the sound pressure level (spl) control register is used to control the volume of the alert transducer. a high-frequency clock signal is used to modulate the normal alert ou tput frequency. this modulation reduces the amplitude of the frequency components in the audible range while adding new frequencies outside the audible range. this feature causes a significant reduction in the spl of the transducer. a broad range of volume control is obtained by altering the duty cycle of the high frequency modulation signal. the spl control register is software programmable to allow users to select different frequencies with different duty cycles. 1000 f osc 10 3276 3200 3840 1001 f osc 20 1638 1600 1920 1010 f osc 40 819 800 960 1011 f osc 80 410 400 480 1100 f osc 14 2341 2285 2743 1101 f osc 28 1170 1143 1371 1110 f osc 56 585 571 686 1111 off v ss v ss v ss address: $0011 bit 7654321bit 0 read:0000 al3 al2 al1 al0 write: reset:00000000 = unimplemented figure 14-1. alert control register (alcr) table 14-1. audio alert tone generator divider ratios (continued) al3?al0 audio alert generator fr equencies at given f osc f osc 32.768 khz 32.000 khz 38.4 khz functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 169 14.3.3 alert data register the alert data register (aldr) bits are: spl7 bit this bit selects between 16-phase duty cycle modul ation if bit spl7 = 0 and 8-phase duty cycle modulation if bit spl7 = 1. spl6 bit this bit selects between the output (dcmod) of the duty cycle modulator when spl6 = 0 and the clock fmodhi when spl6 = 1 to send to the output splclk to modulate the alert output. (see figure 14-3 .) spl5 and spl4 bits these bits are used to control the frequency divider sele ctions (divided by 1, 2, and 4) and, along with bit spl6 in one case where both spl4 and spl5 are high, to select between a cpu clock divided by 8 and the crystal clock. (see table 14-2 .) spl3?spl0 bits these bits control the duty cycle of the modulation signal, as shown in table 14-3 . address: $0012 bit 7654321bit 0 read: spl7 spl6 spl5 spl4 spl3 spl2 spl1 spl0 write: reset:00000000 figure 14-2. alert data register (aldr) table 14-2. clock divider and modulator selections spl6 spl5 spl4 fmodhi splclk 0 0 0 it12/1 dcmod 0 0 01 it12/2 dcmod 0 1 0 it12/4 dcmod 0 1 1 it12/8 dcmod 1 0 0 it12/1 fmodhi 1 0 1 it12/2 fmodhi 1 1 0 it12/4 fmodhi 1 1 1 cgmxclk fmodhi table 14-3. duty cycle selection spl3 spl2 spl1 spl0 duty cycle 8-phase count (spl7 = 1) duty cycle 16-phase count (spl7 = 0) 0 0 0 0 spl disabled spl disabled 0 0 0 1 1/8 high 7/8 low 1/16 high 15/16 low 0 0 1 0 2/8 high 6/8 low 2/16 high 14/16 low 0 0 1 1 3/8 high 5/8 low 3/16 high 13/16 low 0 1 0 0 4/8 high 4/8 low 4/16 high 12/16 low continued on next page alert output generator (alr) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 170 freescale semiconductor figure 14-3. block diagram of spl reduction circuit 0 1 0 1 5/8 high 3/8 low 5/16 high 11/16 low 0 1 1 0 6/8 high 2/8 low 6/16 high 10/16 low 0 1 1 1 7/8 high 1/8 low 7/16 high 9/16 low 1 0 0 0 spl disabled 8/16 high 8/16 low 1 0 0 1 1/8 high 7/8 low 9/16 high 7/16 low 1 0 1 0 2/8 high 6/8 low 10/16 high 6/16 low 1 0 1 1 3/8 high 5/8 low 11/16 high 5/16 low 1 1 0 0 4/8 high 4/8 low 12/16 high 4/16 low 1 1 0 1 5/8 high 3/8 low 13/16 high 3/16 low 1 1 1 0 6/8 high 2/8 low 14/16 high 2/16 low 1 1 1 1 7/8 high 1/8 low 15/16 high 1/16 low table 14-3. duty cycle selection (continued) spl3 spl2 spl1 spl0 duty cycle 8-phase count (spl7 = 1) duty cycle 16-phase count (spl7 = 0) divider 1 2 4 8 m u x m u x cpu xtal clock fmodhi dcmod splclk duty cycle modulator audio signal frequency selection v cc v o spl6 mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 171 chapter 15 liquid crystal display module (lcd) 15.1 introduction the liquid crystal display (lcd) module provides so ftware control for eight backplanes and either 10 or 85 frontplanes. 15.2 features features of the lcd module include: built-in voltage generator charge pump software selectable three, five, or eight backplanes software selectable 10 or 85 frontplanes anti-ghosting capability figure 15-1. lcd driver block diagram m68hc08 davinci internal bus lcd address register lcd data register pointer logic 85 lcd fp 8-bit latches lcd drivers backplane generator voltage generator bp0 bp1 bp6 bp7 fp0 fp1 fp83 fp84 ... ... 4 8 8 data 8 data vcp1 vcp2 vll32 vll clock from timebase circuit vcp3 vcp4 vll12 5 add 5 add liquid crystal display module (lcd) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 172 freescale semiconductor 15.3 functional description this lcd driver circuit has a maximum of eight backplanes (bp) and 85 frontplanes (fp). the output waveform has a maximum output level of 3/2 v ll and is configured with 1/3 bias. the output voltage levels are v ss , 1/2 v ll , v ll , and 3/2 v ll (v ll ? lcd power supply). the bias voltage levels are generated internally from the external inputs v ll , v cp1 ?v cp4 , v ll12 , and v ll32 . for more information on using the lcd voltage converter, see the functional pin description in 15.7 power supply pins (vll, vll12, vll32, and vcp1?vcp4) . 15.4 lcd registers the lcd driver outputs are manipulated through software control of the lcd control register, the lcd address register, and the lcd data register. data is written to each of the 85 frontplanes by writing the fp number to the lcd address register and then writing the data to the lcd data register. 15.4.1 lcd control register the lcd control register (lcdcr) is a read/write regist er containing the control bits to configure the lcd drivers. duty1 and duty0 ? duty cycle select bits these bits enable all fp outputs and select the duty of the lcd driver, enabling the specified number of bp outputs. reset clears these bits, disabli ng lcd waveforms at the outputs. when disabled, an lcd output will be held at v ss . table 15-1 shows the duty cycle selected and the corresponding number of backplanes, as well as the frame rate for the chosen duty cycle. agon ? anti-ghost on bit this bit is used to turn the anti-ghosting feature on or off. when agon = 1, the anti-ghosting feature is enabled. when agon = 0, anti-ghosting is turned off. for additional information, see 15.5 anti-ghosting . this bit is cleared by reset. address: $001a bit 7654321bit 0 read: duty1 duty0 agon dsmin motmd 0 0 0 write: reset:00000000 figure 15-2. lcd control register (lcdcr) table 15-1. duty cycle select duty1?duty0 duty number of backplanes frame rate f osc = 32.000 khz frame rate f osc = 38.4 khz 00 off off off off 01 1/3 3 27.8 hz 33.3 hz 10 1/5 5 25.0 hz 30.0 hz 11 1/8 8 31.25 hz 37.5 hz lcd registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 173 dsmin ? display minimum bit this bit is used to force the data of the lower 75 fp (fp0?fp74) to be 0. this mode is used to enable only part of the display to be on (for example, clock display) without having to rewrite the data on the rest of the display to 0. motmd ? multiplex mode bit this bit can be used to convert the lcd outputs to accommodate multiplexed lcd driver ics (integrated circuits) from fr eescale (mc145000 and mc145001). 1 = freescale (multiplex) mode enabled 0 = standard (lower current consumption) mode enabled 15.4.2 lcd address register the lcd address register (lcdar) is a read/write register used to access the data for each fp register. to access the fp registers, the lcd address is the frontplane pin number converted to hexadecimal. for this implementation of 85 frontplanes, bit 7 is always set to 0. (see table 15-2 .) address: $001b bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 15-3. lcd address register (lcdar) table 15-2. frontplane address assignments pin name address pin name address fp0 fp1 fp2 fp3 fp4 $01 $02 $03 $04 $05 fp45 fp46 fp47 fp48 fp49 $2e $2f $30 $31 $32 fp5 fp6 fp7 fp8 fp9 $06 $07 $08 $09 $0a fp50 fp51 fp52 fp53 fp54 $33 $34 $35 $36 $37 fp10 fp11 fp12 fp13 fp14 $0b $0c $0d $0e $0f fp55 fp56 fp57 fp58 fp59 $38 $39 $3a $3b $3c fp15 fp16 fp17 fp18 fp19 $10 $11 $12 $13 $14 fp60 fp61 fp62 fp63 fp64 $3d $3e $3f $40 $41 continued on next page liquid crystal display module (lcd) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 174 freescale semiconductor 15.4.3 lcd data register each bit in the read/write lcd data r egister (lcddr) is the data to be written out on to the fp pin, as specified in the lcd address register, in the appropriate bp time frame. the correct address must be written into the lcd address register before reading from or writing to the lcd data register. the data in this register is for all the segments controlled by the fp driver. if the user has selected less than eight backplanes, t he upper bits of this register will be unknown. bpx 1 = fp output on during bpx time frame 0 = fp output off during bpx time frame fp20 fp22 fp23 fp24 fp25 $15 $16 $17 $18 $19 fp65 fp66 fp67 fp68 fp69 $42 $43 $44 $45 $46 fp25 fp26 fp27 fp28 fp29 $1a $1b $1c $1d $1e fp70 fp71 fp72 fp73 fp74 $47 $48 $49 $4a $4b fp30 fp31 fp32 fp33 fp34 $1f $20 $21 $22 $23 fp75 fp76 fp77 fp78 fp79 $4c $4d $4e $4f $50 fp35 fp36 fp37 fp38 fp39 $24 $25 $26 $27 $28 fp80 fp81 fp82 fp83 fp84 $51 $52 $53 $54 $55 fp40 fp41 fp42 fp43 fp44 $29 $2a $2b $2c $2d address: $001c bit 7654321bit 0 read: bp7 bp6 bp5 bp4 bp3 bp2 bp1 bp0 write: reset:00000000 figure 15-4. lcd data register (lcddr) table 15-2. frontplane address assignments (continued) pin name address pin name address lcd registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 175 for example, if the segment controlled by fp 1 and bp4 is to be on, follow this sequence: 1. write $02 to the lcd address register. 2. write 1 to bit 4 of the lcd data register. figure 15-5. lcd backplane waveforms ? 3 bp bp0 bp1 bp2 fpx on during bp1 fpx waveform 1/3 duty all bp on/off negative ground +3.0 +2.0 +1.0 0 positive ground +1.0 0 ?1.0 ?2.0 v ll32 v ll v ll12 v ss v ll32 v ll v ll12 v ss on off 1 frame v ll32 v ll v ll12 v ss ?v ll12 ?v ll ?v ll32 fpx data register = $x001 fpx data register = $x111 (on) fpx data register = $x000 (off) segment waveform bp1 ? fpx fpx data register = $xxx1 (on) fpx data register = $xxx0 (off) 27.8 hz liquid crystal display module (lcd) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 176 freescale semiconductor figure 15-6. lcd backplane waveforms ? 5 bp bp0 bp1 bp2 bp3 bp4 fpx on during bp0 fpx waveform 1/5 duty all bp on/off negative ground +3.0 +2.0 +1.0 0 positive ground +1.0 0 ?1.0 ?2.0 v ll32 v ll v ll12 v ss v ll32 v ll v ll12 v ss 1 frame on off v ll32 v ll v ll12 v ss ?v ll12 ?v ll ?v ll32 fpx data register = $xxx0 0001 fpx data register = $xxx1 1111 (on) fpx data register = $xxx0 0000 (off) fpx data register = $xxxx xxx1 (on) fpx data register = $xxxx xxx0 (off) 25.0 hz segment waveform bp0 ? fpx lcd registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 177 figure 15-7. lcd backplane waveforms ? 8 bp bp0 bp1 bp2 bp3 bp4 fpx on during bp0 fpx waveform 1/8 duty all bp on/off bp5 bp7 bp6 v ll32 v ll v ll12 v ss on 1 frame off fpx data register = $0000 0001 fpx data register = $1111 1111 (on) fpx data register = $0000 0000 (off) fpx data register = $xxxx xxx1 (on) fpx data register = $xxxx xxx0 (off) segment waveform bp0 ? fpx 31.25 hz negative ground +3.0 +2.0 +1.0 0 positive ground +1.0 0 ?1.0 ?2.0 v ll32 v ll v ll12 v ss v ll32 v ll v ll12 v ss ?v ll12 ?v ll ?v ll32 liquid crystal display module (lcd) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 178 freescale semiconductor 15.5 anti-ghosting the purpose of the anti-ghosting feature is to provide the user with the option to improve the lcd viewing angle at the expense of display contrast and increas ed power consumption. the level of improvement to the viewing angle as well as the amount of reduction in contrast depends entirely on the display used. the anti-ghosting is performed by taking all frontplane and backplane pins to v ss potential for a short time (~16 s), while the internal muxing circuitry is transitioning. see figure 15-8 for waveforms detailing the anti-ghosting pulses. note the anti-ghosting pulses are not shown in the previous figures. operating i dd current approximately doubles with the use of the anti-ghosting function. this feature generates radiated noise that has been shown to negatively impact rf (radio frequency) performance in some applications. rf testing should be completed before implementing anti-ghosting. figure 15-8. lcd backplane waveforms with anti-ghosting ? 3 bp bp0 bp1 bp2 fpx on during bp0 fpx waveform 1/3 duty all bp on/off negative ground +3.0 +2.0 +1.0 0 positive ground +1.0 0 ?1.0 ?2.0 v ll32 v ll v ll12 v ss v ll32 v ll v ll12 v ss on off 1 frame v ll32 v ll v ll12 v ss ?v ll12 ?v ll ?v ll32 fpx data register = $x001 fpx data register = $x111 (on) fpx data register = $x000 (off) segment waveform bp0 ? fpx fpx data register = $xxx1 (on) fpx data register = $xxx0 (off) 27.8 hz ~16 s ~5.9 ms anti-ghosting pulse v ll32 v ll v ll12 v ss software examples mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 179 15.6 software examples this example shows a routine which loads the lcd da ta register with information for each frontplane. ************************************************************************ * * lcd register definitions * lcdcr equ $1a lcd control register lcdar equ $1b lcd address register lcddr equ $1c lcd data register org $8000 * * load data into correct data registers * ldx #45 load correct number of data registers datald stx lcdar point to the desired data register lda data-1,x fetch data sta lcddr store data decx point to next register bne datald continue until all data registers full * * turn on display * ldx #$c0 stx lcdcr configure w/ 8 bps bra * loop here; hold display * *message table - displays " display " in nine 5x7 dot matrix characters *(0 = off, 1 = on) * bp0 f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f . . . * bp0 p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p . . . * bp0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 . . . * bp0 0 0 0 0 0 01 1 1 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 . . . * * bp0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 . . . * bp1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 . . . * bp2 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 . . . * bp3 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 1 0 1 1 1 1 0 1 0 0 0 0 . . . * bp4 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 . . . * bp5 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 . . . * bp6 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 . . . data equ * ** ** fcb $00,$00,$00,$00,$00 **d** fcb $7f,$41,$41,$22,$1c **i** fcb $00,$41,$7f,$41,$00 **s** fcb $46,$49,$49,$49,$31 **p** fcb $7f,$09,$09,$09,$06 **l** fcb $7f,$40,$40,$40,$40 **a** fcb $7e,$11,$11,$11,$7e **y** fcb $07,$08,$70,$08,$07 ** ** fcb $00,$00,$00,$00,$00 liquid crystal display module (lcd) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 180 freescale semiconductor 15.7 power supply pins (v ll , v ll12 , v ll32 , and v cp1 ?v cp4 ) these are power supply pins for the lcd voltage converter. when using the internal lcd voltage converter, the pins should be connected as shown in figure 15-9 . figure 15-9. lcd voltage converter connections if an external voltage supply is used to power the lcd module, the appropriate voltages should be applied to the v ll , v ll12 ( 1 / 2 v ll ) and v ll32 ( 3 / 2 v ll ) pins. v cp1 ?v cp4 should be left floating. v ll v ll12 v ll32 vcp1 vcp2 vcp3 v ll 0.1 f, used for supply bypass vcp4 0.1 f 0.1 f 0.1 f 0.1 f mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 181 chapter 16 timer interface module (tim) 16.1 introduction this section describes the timer interface module (t im). the tim is a 4-channel timer that provides a timing reference with input capture, output compare, and pulse-width- modulation functions. figure 16-1 is a block diagram of the tim. note references to dma and associated f unctions are only valid if the mcu has a dma module. this mcu does not have the dma function. any dma-related register bits should be left in their reset state for normal mcu operation. 16.2 features features of the tim include: modular architecture four input capture/output compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tim clock input: ? seven-frequency internal bus clock prescaler selection ? external tim clock input (4-mhz maximum frequency) free-running or modulo up-count operation toggle any channel pin on overflow timer counter stop and reset bit note because no input or output pins are available for the timer module, the input capture functions are disabled. however, for the output compare function, when the counter reaches the value in the selected channel register, the timer can generate an interrupt to cpu. but it can?t set, clear, or toggle the timer compare pin. ignore all references to tchx pins. see 16.4 interrupts for more information. note the shaded boxes in figure 16-1 are not implemented in this module. all references to these blocks should be ignored. tclk is a floating pin. do not set the ps2?ps0 bits in the tim status and control register to select tclk input. timer interface module (tim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 182 freescale semiconductor figure 16-1. tim block diagram prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie inter- 16-bit comparator 16-bit latch tch1h:tch1l 16-bit comparator 16-bit latch tch2h:tch2l 16-bit comparator 16-bit latch tch3h:tch3l channel 0 channel 1 channel 2 channel 3 tmodh:tmodl trst tstop tov0 ch0ie dma0s ch0f els1b els1a tov1 ch1ie dma1s ch1max ch1f els2b els2a tov2 ch2ie dma2s ch2max ch2f els3b els3a tov3 ch3ie dma3s ch3max ch3f ch0max ms0b ms2b 16-bit counter internal bus bus clock ms1a ms2a ms3a tclk tch0 tch1 tch2 tch3 logic rupt logic inter- rupt logic logic inter- rupt logic logic inter- rupt logic logic inter- rupt logic features mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 183 addr. register name bit 7654321bit 0 $0020 tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00000000 $0021 unimplemented $0022 tim counter register high (tcnth) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0023 tim counter register low (tcntl) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 $0024 tim counter modulo register high (tmodh) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0025 tim counter modulo register low (tmodl) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 $0026 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0027 tim channel 0 register high (tch0h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0028 tim channel 0 register low (tch0l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 $0029 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $002a tim channel 1 register high (tch1h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $002b tim channel 1 register low (tch1l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 $002c tim channel 2 status and control register (tsc2) read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 = unimplemented figure 16-2. tim i/o register summary timer interface module (tim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 184 freescale semiconductor 16.3 functional description figure 16-1 shows the structure of the tim. the central co mponent of the tim is the 16-bit timer counter that can operate as a free-running counter or a modulo up-counter. the timer counter provides the timing reference for the input capture and output compare functions. the timer counter modulo registers, tmodh and tmodl, control the modulo value of the timer counter. software can read the timer counter value at any time without affecting the counting sequence. the four tim channels are programmable independently as input capture or output compare channels. 16.3.1 timer counter prescaler the tim clock source can be one of the seven prescaler outputs or the tim clock pin, tclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps2?ps0, in the timer status and control register select the tim clock source. note this device does not have a tclk pin. 16.3.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the tim latches the contents of the timer counter into the timer channel registers, tchxh and tchxl. the polarity of the active edge is programmable. input capture latency can be up to th ree bus clock cycles. input captures can generate tim cpu interrupt requests. note this device does not have input capture functionality. $002d tim channel 2 register high (tch2h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $002e tim channel 2 register low (tch2l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 $002f tim channel 3 status and control register (tsc3) read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 $0030 tim channel 3 register high (tch3h) read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0031 tim channel 3 register low (tch3l) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 addr. register name bit 7654321bit 0 = unimplemented figure 16-2. tim i/o register summary (continued) functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 185 16.3.3 output compare with the output compare function, the tim can generat e a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the ch annel pin. output compares can generate tim cpu interrupt requests or tim dma service requests. note this device does not have output compare pins. 16.3.3.1 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 16.3.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the timer channel registers. an unsynchronized write to the timer channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a timer over flow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the timer may pass the new value before it is written. use these methods to synchronize unbuffered ch anges in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable channel x timer overflow interrupts and write the new value in the timer overflow interrupt routine. the timer overflow interrupt occurs at the end of the current counter overflow period. writ ing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 16.3.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the timer channel registers of the linked pair alternately control the output. setting the ms0b bit in timer channel 0 status and control register (tsc0) links channel 0 and channel 1. the output compare value in the timer channel 0 regist ers initially controls the output on the tch0 pin. writing to the timer channel 1 registers enables the timer channel 1 registers to synchronously control the output after the timer overflows. at each subsequent ov erflow, the timer channel registers (0 or 1) that control the output are the ones written to last. ts c0 controls and monitors the buffered output compare function, and timer channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the tch2 pin. the timer channel registers of the linked pair alternately control the output. setting the ms2b bit in timer channel 2 status and control register (tsc2) links channel 2 and channel 3. the output compare value in the timer channel 2 regist ers initially controls the output on the tch2 pin. writing to the timer channel 3 registers enables the timer channel 3 registers to synchronously control the timer interface module (tim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 186 freescale semiconductor output after the timer overflows. at each subsequent ov erflow, the timer channel registers (2 or 3) that control the output are the ones written to last. ts c2 controls and monitors the buffered output compare function, and timer channel 3 status and control regi ster (tsc3) is unused. in buffered output compare operation, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. 16.3.4 pulse-widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the timer counter modulo registers determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the timer counter modulo registers. the time between overflows is the period of the pwm signal. as figure 16-3 shows, the output compare value in the time r channel registers determines the pulse width of the pwm signal. the time between overflow and out put compare is the pulse width. program the tim to clear the channel pin on output compare if the stat e of the pwm pulse is logic 1. program the tim to set the pin if the state of the pwm pulse is logic 0. figure 16-3. pwm period and pulse width the value in the timer counter modulo registers and the selected prescaler output determine the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the timer counter modulo registers produces a pwm period of 256 times the internal bus clock period. the value in the timer channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the timer channel registers produces a duty cycle of 128/256 or 50%. note this device does not have channel pins for pwm. ptex/tchx period pulse width overflow overflow overflow output compare output compare output compare functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 187 16.3.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 16.3.4 pulse-width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value cu rrently in the timer channel registers. an unsynchronized write to the timer channel r egisters to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a timer overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the timer may pass the new value before it is written. use these methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x timer overflow interrupts and write the new value in the timer overflow interrupt routine. the timer overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 16.3.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the timer channel registers of the linked pair alte rnately control the pulse width of the output. setting the ms0b bit in timer channel 0 status and control register (tsc0) links channel 0 and channel 1. the timer channel 0 registers initially control the pulse width on the tch0 pin. writing to the timer channel 1 registers enables the timer channel 1 registers to sy nchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the timer channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 cont rols and monitors the buffered pwm function, and timer channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pi n if the timer pad is shared with the i/o pad. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the tch2 pin. the timer channel registers of the linked pair alte rnately control the pulse width of the output. setting the ms2b bit in timer channel 2 status and control register (tsc2) links channel 2 and channel 3. the timer channel 2 registers initially control the pulse width on the tch2 pin. writing to the timer channel 3 registers enables the timer channel 3 registers to sy nchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the timer channel registers (2 or 3) that control the pulse width are the ones written to last. tsc2 cont rols and monitors the buffered pwm function, and timer channel 3 status and control register (tsc3) is unused. timer interface module (tim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 188 freescale semiconductor note in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered pwm signals. 16.3.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use this initialization procedure: 1. in the timer status and control register (tsc): a. stop the timer counter by setting the timer stop bit, tstop. b. reset the timer counter by se tting the timer reset bit, trst. 2. in the timer counter modulo registers (tmodh and tmodl), write the value for the required pwm period. 3. in the timer channel x registers (tchxh and tchx l), write the value for the required pulse width. 4. in timer channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode se lect bits, msxb:msxa. (see table 16-2 .) b. write 1 to the toggle on overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb and elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 16-2 .) note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the timer status control register (tsc), clear the timer stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the timer channel 0 registers (tch0h and tch0l) initially control the buffered pwm output. timer status control register 0 (tscr0) controls and monitors the pwm si gnal from the linked channels. ms0b takes priority over ms0a. setting ms2b links channels 2 and 3 and configures them for buffered pwm operation. the timer channel 2 registers (tch2h and tch2l) initially control the pwm output. timer status control register 2 (tscr2) controls and monitors the pwm signal from th e linked channels. ms2b takes priority over ms2a. clearing the toggle on overflow bit, tovx, inhibits ou tput toggles on timer overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the chxmax bit generates a 100% duty cycle output. (see 16.8.4 timer channel status and control registers .) interrupts mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 189 16.4 interrupts the tim sources can generate these interrupt requests: tim overflow flag (tof) ? tof is set when the tim counter value matches the value in the tim counter modulo registers. the tim overflow in terrupt enable bit, toie, enables the tof flag to generate tim overflow cpu interrupt requests. to f and toie are in the tim status and control register tim channel flags (ch3f?ch0f) ? chxf is set w hen an input capture or output compare occurs on channel x. the channel x interrupt enable bit, chxie, enables the chxf flag to generate tim channel x cpu interrupt requests. chxf and chxie are in the tim channel x status and control register. 16.5 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 16.5.1 wait mode the tim remains active after the execution of a wait instruction. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if the tim is not required to bring the mcu out of wait mode, reduce power consumption by stopping the tim before executing the wait instruction. 16.5.2 stop mode the tim is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the timer counter. timer operation resumes when the mcu exits stop mode after an external interrupt. note this device does not function in stop mode. 16.6 tim during break interrupts a break interrupt stops the timer counter. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see 9.4.1 break status and control register .) to allow software to clear status bits during a break in terrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it rema ins cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o register s during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. timer interface module (tim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 190 freescale semiconductor 16.7 i/o signals tclk is an external clock input to the timer prescaler. the four timer channel i/o pins are tch0, tch1, tch2, and tch3. note this device does not have external timer pins. 16.7.1 tim clock pin (tclk) tclk is an external clock input th at can be the clock source for the timer counter instead of the prescaled internal bus clock. select the tclk input by writing logic 1s to the three prescaler select bits, ps2?ps0. (see 16.8.1 timer status and control register .) the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is: bus frequency 2 16.7.2 timer channel i/o pins (tch0?tch3) each channel i/o pin is programmable independently as an input capture pin or an output compare pin. tch0 and tch2 can be configured as buffered output compare or buffered pwm pins. 16.8 i/o registers these i/o registers control and monitor operation of the tim: timer status and control register (tsc) timer dma select register (tdma) timer control registers (tcnth and tcntl) timer counter modulo registers (tmodh and tmodl) timer channel status and control registers (tsc0, tsc1, tsc2, and tsc3) timer channel registers (tch0h, tch0l, tch1h, tch1l, tch2h, tch2l, tch3h, and tch3l) 16.8.1 timer status and control register the timer status and control register (tsc): enables timer overflow interrupts flags timer overflows stops the timer counter resets the timer counter and prescaler prescales the timer counter clock 1 bus frequency ------------------------------------- t su + i/o registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 191 tof ? timer overflow flag bit this read/write flag is set when the timer counter reaches the modulo value programmed in the timer counter modulo registers. clear tof by reading the timer status and control register when tof is set and then writing a logic 0 to tof. if another timer overflow occurs before the clearing sequence is complete, then writing logic 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears th e tof bit. writing a logic 1 to tof has no effect. 1 = timer counter has reached modulo value. 0 = timer counter has not reached modulo value. toie ? timer overflow interrupt enable bit this read/write bit enables timer overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = timer overflow interrupts enabled 0 = timer overflow interrupts disabled tstop ? timer stop bit this read/write bit stops the timer counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the timer counter until software clears the tstop bit. 1 = timer counter stopped 0 = timer counter active note do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. trst ? timer reset bit setting this write-only bit resets the timer counter and the timer prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the timer counter is reset and always reads as logic 0. reset clears the trst bit. 1 = prescaler and timer counter cleared 0 = no effect note setting the tstop and trst bits simultaneously stops the timer counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select either the pte3/tclk pin or one of the seven prescaler outputs as the input to the timer counter as table 16-1 shows. reset clears the ps2?ps0 bits. note tclk is a floating input pin. do not select ps2?ps0 = 111. address: $0020 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00000000 = unimplemented figure 16-4. timer status and control register (tsc) timer interface module (tim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 192 freescale semiconductor 16.8.2 timer counter registers the two read-only timer counter registers contain the high and low bytes of the value in the timer counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl). subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the timer counter registers. setting the timer reset bit (trst) also clears the timer counter registers. table 16-1. prescaler selection ps2?ps0 tim clock source 000 internal bus clock 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 pte3/tclk address: $0022 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 = unimplemented figure 16-5. timer counter register high (tcnth) address: $0023 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 16-6. timer counter register low (tcntl) i/o registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 193 16.8.3 timer modulo registers the read/write timer modulo registers contain the m odulo value for the timer counter. when the timer counter reaches the modulo value, the overflow flag (tof) becomes set, and the timer counter resumes counting from $0000 at the next clock. the tof bit and overflow interrupts are inhibited after a write to the high byte (tmodh) until the low byte (tmodl) is written. reset sets the timer modulo registers. note reset the timer counter before writing to the timer modulo registers. 16.8.4 timer channel status and control registers each of the timer channel status and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on timer overflow selects 100% pwm duty cycle address: $0024 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 figure 16-7. timer modulo register high (tmodh) address: $0025 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 16-8. timer modulo register low (tmodl) timer interface module (tim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 194 freescale semiconductor chxf? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the timer counter registers matches the va lue in the timer channel x registers. when tim cpu interrupt requests are enabled (chxie:dmaxs = 1:0), clear chxf by reading timer channel x status and control register with chxf set and then writing a logic 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. when tim dma service requests are enabled (chxie:dmaxs = 1:1), clear chxf by reading or writing to the low byte of the timer channel x registers (tchxl). reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x address: $0026 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 figure 16-9. timer channel 0 status and control register (tsc0) address: $0029 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 16-10. timer channel 1 status and control register (tsc1) address: $002c bit 7654321bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 figure 16-11. timer channel 2 status and control register (tsc2) address: $002f bit 7654321bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 = unimplemented figure 16-12. timer channel 3 status and control register (tsc3) i/o registers mc68hc08lk60 ? mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 195 chxie ? channel x interrupt enable bit this read/write bit enables tim cpu interrupts service requests on channel x. the dmaxs bit in the timer dma select register selects channel x tim d ma service requests or tim cpu interrupt requests. note tim dma service requests cannot be used in buffered pwm mode. in buffered pwm mode, disable tim dma service requests by clearing the dmaxs bit in the timer dma select register. reset clears the chxe bit. 1 = channel x cpu interrupt requests and dma service requests enabled 0 = channel x cpu interrupt requests and dma service requests disabled note reading the high byte of the timer channel x registers (tchxh) inhibits the chxf flag until the low byte (tchxl) is read. msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the timer channel 0 and timer channel 2 status and control regi sters. setting ms0b disables the channel 1 status and control register. setting ms2b disables the channel 3 status and control register. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. (see table 16-2 .) 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin. (see table 16-2 .). reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the timer status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/ write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port e, and pin tchx is available as a general-purpose i/o pin. table 16-2 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. timer interface module (tim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 196 freescale semiconductor note before enabling a timer channel register for input capture operation, make sure that the tchx pin is stable for at least two bus clocks. tovx ? toggle on overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the timer counter overflows. when c hannel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on timer counter overflow. 0 = channel x pin does not toggle on timer counter overflow. note when tovx is set, a timer counter overflow takes precedence over a channel x output compare if both occur at the same time. reading the high byte of the timer channel x registers prevents the channel x pin from toggling until the low byte is read. chxmax ? channel x maximum (100%) pwm duty cycle bit this read/write bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 16-13 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. table 16-2. mode, edge, and level selection msxb:msxa elsxb:elsx a mode configuration x0 00 output preset set initial output level high x1 00 set initial output level low xx 00 ? tchx pin under port control 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge xx 00 ? tchx pin under port control; initial output low 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare xx 00 ? tchx pin under port control (1) 1. initial output high if msxa = 0. initial output low if msxa = 1. 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare i/o registers mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 197 figure 16-13. chxmax latency 16.8.5 timer channel registers the timer channel registers (tch0h/l?tch3h/l) are read /write registers containing the captured timer counter value of the input capture function or the ou tput compare value of the output compare function. the state of the timer channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading the high byte of the timer channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the timer channel x registers (tchxh) inhibits output compares until the low byte (tchxl) is written. address: $0027 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 figure 16-14. timer channel 0 register high (tch0h) address: $0028 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 16-15. timer channel 0 register low (tch0l) address: $002a bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 figure 16-16. timer channel 1 register high (tch1h) output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare timer interface module (tim) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 198 freescale semiconductor address: $002b bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 16-17. timer channel 1 register low (tch1l) address: $002d bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 figure 16-18. timer channel 2 register high (tch2h) address: $002e bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 16-19. timer channel 2 register low (tch2l) address: $0030 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 figure 16-20. timer channel 3 register high (tch3h) address: $0031 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 16-21. timer channel 3 register low (tch3l) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 199 chapter 17 input/output (i/o) ports 17.1 introduction twenty-four bidirectional input/output (i/o) pins form three parallel ports. all i/o pins are programmable as inputs or outputs. note connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: ptc7 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 figure 17-1. i/o port register summary input/output (i/o) ports mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 200 freescale semiconductor 17.2 port a port a is an 8-bit, general-purpose, bidirectional i/o port. 17.2.1 port a data register the port a data register (pta) contains a data latch for each of the eight port a pins. pta7?pta0 ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction regi ster a. reset has no effect on port a data. 17.2.2 data dir ection register a data direction register a (ddra) determines whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables the output buffer for the corresponding port a pin; a logic 0 disables the output buffer. ddra7?ddra0 ? data direction register a bits these read/write bits control port a data directio n. reset clears ddra7?ddra0, configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note avoid glitches on port a pins by writin g to the port a data register before changing data direction regist er a bits from 0 to 1. figure 17-4 shows the port a i/o logic. address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset figure 17-2. port a data register (pta) address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 17-3. data direction register a (ddra) port b mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 201 figure 17-4. port a i/o circuit when bit ddrax is a logic 1, reading address $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-1 summarizes the operation of the port a pins. 17.3 port b port b is an 8-bit, general-purpose, bidirectional i/o port. 17.3.1 port b data register the port b data register (ptb) contains a data latch for each of the eight port b pins. ptb7?ptb0 ? port b data bits these read/write bits are software-programmable. data direction of each port b pin is under the control of the corresponding bit in data direction regi ster b. reset has no effect on port b data. the port b interrupt enable bits, ptb7ie?ptb0ie, in the port b interrupt control register (ptbicr) enable the port b pins as external interrupt pins. see chapter 11 external interrupt module (irq) . table 17-1. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddra7?ddra0 pin pta7?pta0 (3) 3. writing affects data register , but does not affect input. 1 x output ddra7?ddra0 pta7?pta0 pta7?pta0 address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset figure 17-5. port b data register (ptb) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus input/output (i/o) ports mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 202 freescale semiconductor 17.3.2 data dir ection register b data direction register b (ddrb) determines whether each port b pin is an input or an output. writing a logic 1 to a ddrb bit enables the output buffer for the corresponding port b pin; a logic 0 disables the output buffer. ddrb7?ddrb0 ? data direction register b bits these read/write bits control port b data direction. reset clears ddrb7?ddrb0, configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note avoid glitches on port b pins by writin g to the port b data register before changing data direction regist er b bits from 0 to 1. figure 17-7 shows the port b i/o logic. figure 17-7. port b i/o circuit when bit ddrbx is a logic 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-2 summarizes the operation of the port b pins. address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 17-6. data direction register b (ddrb) table 17-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrb7?ddrb0 pin ptb7?ptb0 (3) 3. writing affects data register, but does not affect input. 1 x output ddrb7?ddrb0 ptb7?ptb0 ptb7?ptb0 read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus port c mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 203 17.4 port c port c is an 8-bit, general-purpose, bidirectional i/o port. 17.4.1 port c data register the port c data register (ptc) contains a data latch for each of the eight port c pins. ptc7?ptc0 ? port c data bits these read/write bits are software-programmable. da ta direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. 17.4.2 data dir ection register c data direction register c (ddrc) determines whether ea ch port c pin is an input or an output. writing a logic 1 to a ddrc bit enables the output buffer for t he corresponding port c pin; a logic 0 disables the output buffer. ddrc7?ddrc0 ? data direction register c bits these read/write bits control po rt c data direction. reset clears ddrc7?ddrc0, configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note avoid glitches on port c pins by writin g to the port c data register before changing data direction regist er c bits from 0 to 1. figure 17-10 shows the port c i/o logic. address: $0002 bit 7654321bit 0 read: ptc7 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset figure 17-8. port c data register (ptc) address: $0006 bit 7654321bit 0 read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 figure 17-9. data direction register c (ddrc) input/output (i/o) ports mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 204 freescale semiconductor figure 17-10. port c i/o circuit when bit ddrcx is a logic 1, r eading address $0002 reads the ptcx data latch. when bit ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-3 summarizes the operation of the port c pins. table 17-3. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrc7?ddrc0 pin ptc7?ptc0 (3) 3. writing affects data regist er, but does not affect input. 1 x output ddrc7?ddrc0 ptc7?ptc0 ptc7?ptc0 read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 205 chapter 18 monitor rom (mon) 18.1 introduction this section describes the monitor read-only memory (rom). the monitor rom (mon) allows complete testing of the mcu through a single-wire interface with a host computer. 18.2 features features of the mon include: normal user-mode pin functionality one pin dedicated to serial communicati on between monitor rom and host computer standard mark/space non-return-to-zero (nrz) communication with host computer 4800-baud to 28.8-kbaud communication with host computer execution of code in random-a ccess memory (ram) or rom 18.3 functional description the monitor rom receives and executes commands from a host computer. figure 18-1 shows a sample circuit used to enter monitor mode and communic ate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute host-computer code in ram while all mcu pins re tain normal operating mode functions. all communication between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pullup resistor. monitor rom (mon) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 206 freescale semiconductor figure 18-1. monitor mode circuit + + + + 10 m ? x1 v dd v dda v dd + v hi v dd mc145407 mc74hc125 68hc(9)08 rst irq1 irq2 v dda cgmxfc osc1 osc2 ev ss v ss v dd pta0 v dd 10 k ? 0.1 f 0.1 f 10 k ? 10 ? 6 5 4 3 2 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 20 pf 20 pf 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 4.9152 mhz 10 k ? ptc3 v dd 10 k ? b a note: position a ? bus clock = cgmxclk 4 or cgmvclk 4 position b ? bus clock = cgmxclk 2 (see note.) 5 6 ptc0 ptc1 v dd 10 k ? functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 207 18.3.1 entering monitor mode table 18-1 shows the pin conditions for entering monitor mode. enter monitor mode by either: executing a software interrupt instruction (swi) or applying a logic 0 and then a logic 1 to the rst pin the mcu sends a break signal (10 consecutive logic 0s) to the host computer, indicating that it is ready to receive a command. the break signal also provides a timing reference to allow the host to determine the necessary baud rate. monitor mode uses alternate vectors for reset, swi, and break interrupt. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. the cop module is disabled in monitor mode as long as v dd +v hi is applied to either the irq1 pin or the rst pin. see chapter 6 system integration module (sim) for more information on modes of operation. note holding the ptc3 pin low when enter ing monitor mode causes a bypass of a divide-by-two stage at the oscillator. the cgmout frequency is equal to the cgmxclk frequency, and the osc1 input directly generates internal bus clocks. in this case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. table 18-2 is a summary of the differences between user mode and monitor mode. table 18-1. mode selection irq1 pin ptc0 pin ptc1 pin pta0 pin ptc3 pin mode cgmout bus frequency v dd + v hi 1011monitor or v dd + v hi 1010monitor cgmxclk table 18-2. mode differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor (1) 1. if pta0 is low out of reset, the cp u performs a jump to ram for burn-in. disabled (2) 2. if the high voltage (v dd + v hi ) is removed from the irq1 pin or the rst pin, the sim asserts its cop enable output. $fefe $feff $fefc $fefd $fefc $fefd cgmxclk 2 ----------------------------- cgmvclk 2 ----------------------------- cgmout 2 -------------------------- cgmout 2 -------------------------- monitor rom (mon) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 208 freescale semiconductor 18.3.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) ma rk/space data format. (see figure 18-2 and figure 18-3 .) the data transmit and receive rate can be anywher e from 4800 baud to 28.8 kbaud. transmit and receive baud rates must be identical. figure 18-2. monitor data format figure 18-3. sample monitor waveforms 18.3.3 echoing as shown in figure 18-4 , the monitor rom immediately echoes each received byte back to the pta0 pin for error checking. any result of a command appears after the echo of the last byte of the command. figure 18-4. read transaction 18.3.4 break signal a start bit followed by nine low bits is a break signal. (see figure 18-5 .) when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits before echoing the break signal. figure 18-5. break transaction bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 addr. high read read addr. high addr. low addr. low data echo sent to monitor result 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit 2-stop bit delay before 0 echo functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 209 the monitor rom uses these commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) table 18-3. read (read memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence table 18-4. write (write memory) command description write byte to memory operand specifies 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence addr. high read read addr. high addr. low addr. low data echo sent to monitor result addr. high write write addr. high addr. low addr. low data echo sent to monitor data monitor rom (mon) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 210 freescale semiconductor a sequence of iread or iwrite commands can acce ss a block of memory sequentially over the full 64-kbyte memory map. table 18-5. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence table 18-6. iwrite (indexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence data iread iread data echo sent to monitor result data iwrite iwrite data echo sent to monitor functional description mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 211 table 18-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointe r in high byte:low byte order opcode $0c command sequence table 18-8. run (run user program) command description executes rti instruction operand none data returned none opcode $28 command sequence sp high readsp readsp sp low echo sent to monitor result run run echo sent to monitor monitor rom (mon) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 212 freescale semiconductor 18.3.5 baud rate with a 4.9152-mhz crystal and the ptc3 pin at lo gic 1 during reset, data is transferred between the monitor and host at 4800 baud. if the ptc3 pin is at logic 0 during reset, the monitor baud rate is 9600. when the cgm output, cgmout, is driven by the pl l, the baud rate is determined by the mul11?mul0 bits in the pll multiplier registers. see chapter 7 clock generator module (cgmb) . table 18-9. monitor baud rate selection vco frequency multiplier (n) 123456 monitor baud rate 4800 9600 14,400 19,200 24,000 28,800 mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 213 chapter 19 keyboard interrupt (kbi) module 19.1 introduction the keyboard interrupt (kbi) module provides eigh t independently maskable external interrupt pins. 19.2 features features include: eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask the keyboard interrupt module shares the 8-bit bidirectional i/o port with port b. 19.3 functional description writing to the kbie7?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port b pin as a keyboard interrupt pi n. enabling a keyboard interrupt pin also enables its internal pullup device. a logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt request is latched when one or more keyboard pins goes low after all were high. vector fetch or software clear a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software can generate the interrupt acknowledge signal by writin g a logic 1 to the ack2, irq2 interrupt request acknowledge bit in the irq status and control register (iscr). the ack2 bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ack2 bit in an interrupt service rout ine can also prevent spurious interrupts due to noise. setting ack2 does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ack2 bit latches another interrupt request. if the keyboard interrupt mask bit, imask2, is clear, the cpu loads the program coun ter with the vector address at locations $ffd2 and $ffd3. see 19.6.1 irq status and control register . return of all enabled keyboard interrupt pins to logic 1 as long as any enabled keyboard interrupt pin is at l ogic 0, the keyboard interrupt request remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. reset clears the keyboard interrupt request. the pin2 bit in the iscr can be used to see if a pendi ng interrupt exists. the pin2 bit is not affected by the keyboard interrupt mask bit imask2. see 19.6.1 irq status and control register . keyboard interrupt (kbi) module mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 214 freescale semiconductor figure 19-1. block diagram ptb7 kbie7 ptb7 pullup enable ptb0 kbie1 ptb0 pullup enable irq2 pin2 irq2dis ack2 dq ck clr v dd mode2 imask2 irq2/keyboard interrupt latch irq2/kbi interrupt request synchronizer initialization mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 215 to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. note setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a logic 0 for software to read the pin. 19.4 initialization when a keyboard interrupt pin is enabled, it takes time fo r the internal pullup to reach a logic 1. therefore, a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setti ng the imask2 bit in the iscr. see 19.6.1 irq status and control register . 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ack2 bit in the iscr to clear any false interrupts. see 19.6.1 irq status and control register . 4. clear the imask2 bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setti ng the appropriate ddrb bits in data direction register b. 2. write logic 1s to the appropriate port b data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 19.5 wait mode the keyboard interrupt module remains active in wait mode. clearing the iask2 bit in the iscr enables keyboard interrupt requests to bring the mcu out of wait mode. 19.6 i/o registers these registers control and monitor operation of the keyboard interrupt module: irq status and control register (iscr) keyboard interrupt enable register (kbier) 19.6.1 irq status and control register see 11.5 irq status and control register . keyboard interrupt (kbi) module mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 216 freescale semiconductor 19.6.2 keyboard inte rrupt enable register the keyboard interrupt enable register enables or disables each port b pin to operate as a keyboard interrupt pin. kbie7?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corre sponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = pbx pin enabled as keyboard interrupt pin 0 = pbx pin not enabled as keyboard interrupt pin address: $0003 bit 7654321bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 19-2. keyboard interrupt enable register (kbier) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 217 chapter 20 preliminary electrical specifications 20.1 introduction this section contains preliminary electrical and timing specifications. these values are design targets and have not yet been tested. 20.2 absolute maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in this table. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . note this device is not guaranteed to operate properly at the maximum ratings. refer to 20.5 3.0 volt 10% dc electrical characteristics and 20.6 2.0 volt 10% dc electrical characteristics for guaranteed operating conditions. electrostatic discharge (esd) protec tion is provided on each pin to 2000 volts using the human body model of 100 pf and 1500 ohms. using the machine model, esd protection is provided to 200 volts at 100 pf and 0ohms. rating symbol value unit supply voltage v dd ?0.3 to +3.6 v input voltage v in v ss ?0.3 to v dd +0.3 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma note: voltages are referenced to v ss . preliminary electrical specifications mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 218 freescale semiconductor 20.3 functional operating range 20.4 thermal characteristics rating symbol value (1) 1. tested and guaranteed at room temperature only unit operating temperature range t a ?20 to +65 c operating voltage range (2) 2. lcd charge pump optimized for given ranges v dd 2.0 10% 3.0 10% v lcd operating voltage range (3) 3. v ll does not have to equal v dd . v ll 2.0 10% 3.0 10% v characteristic symbol value unit thermal resistance, 160 bga mc68hc08lk60 mc68hc908lk60 ja 61 50 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the dev ice. k can be determined from a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c) + (p d 2 x ja ) w/ c average junction temperature t j t a = p d ja c maximum junction temperature t jm 100 c 3.0 volt 10% dc electrical characteristics mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 219 20.5 3.0 volt 10% dc electrical characteristics characteristic (1) 1. v dd = 3.0 vdc 10%, v ss = 0 vdc, t a = ?20 c to +65 c, unless otherwise noted. symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. max unit output high voltage (i load = ?0.4 ma) all pins v oh 0.7 x v dd ??v output low voltage (i load = 0.8 ma) all pins v ol ?? 0.3 x v dd v input high voltage all ports, irqs, reset, osc1 v ih 0.7 x v dd ? v dd v input low voltage all ports, irqs, reset, osc1 v il v ss ? 0.3 x v dd v monitor mode entry voltage v hi ?? v dd v v dd supply current run (3) wait (4) 3. run (operating) i dd measured using external square wave clock source (f op = 4.1 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f op = 4.1 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . measured with pll, lcd, and tbm disabled. i dd ? ? ? ? 4 2 ma i/o ports high-impedance leakage current i il ?? 10 a input current i in ??1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (5) 5. maximum is highest vo ltage that por is guaranteed. v por 0?200mv por reset voltage (6) 6. maximum is highest vo ltage that por is possible. v porrst 0 700 800 mv por rise time ramp rate (7) 7. if minimum v dd is not reached before the internal por reset is releas ed, rstb must be driven low externally until minimum v dd is reached. r por 0.02 ? ? v/ms preliminary electrical specifications mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 220 freescale semiconductor 20.6 2.0 volt 10% dc electrical characteristics characteristic (1) 1. v dd = 2.0 vdc 10%, v ss = 0 vdc, t a = ?20 c to +65 c, unless otherwise noted. symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. max unit output high voltage (i load = ?0.4 ma) all pins v oh 0.7 x v dd ??v output low voltage (i load = 0.8 ma) all pins v ol ?? 0.3 x v dd v input high voltage all ports, irqs, reset, osc1 v ih 0.7 x v dd ? v dd v input low voltage all ports, irqs, reset, osc1 v il v ss ? 0.3 x v dd v monitor mode entry voltage v hi ?? v dd v v dd supply current run (3) wait (4) 3. run (operating) i dd measured using external square wave clock source (f op = 2 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f op = 2 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . measured with pll, lcd, and tbm disabled. i dd ? ? ? ? 2 1 ma i/o ports high-impedance leakage current i il ?? 10 a input current i in ??1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (5) 5. maximum is highest vo ltage that por is guaranteed. v por 0?200mv por reset voltage (6) 6. maximum is highest vo ltage that por is possible. v porrst 0 700 800 mv por rise time ramp rate (7) 7. if minimum v dd is not reached before the internal por reset is releas ed, rstb must be driven low externally until minimum v dd is reached. r por 0.02 ? ? v/ms 3.0 volt 10% control timing mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 221 20.7 3.0 volt 10% control timing 20.8 2.0 volt 10% control timing characteristic (1) 1. v dd = 3.0 vdc 10%, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v ss unless otherwise noted symbol min max unit frequency of operation, (2) crystal option 2. see 20.11 pll2p12m electrical specifications for more information. f osc 32 100 khz internal operating frequency f op ?4.0mhz internal bus cycle time t cyc ? 250 ns reset input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized; it is possible for a smaller pulse width to cause a reset. t irl 125 ? ns irq interrupt pulse width low, (4) edge-triggered 4. minimum pulse width is for guaranteed interrupt; it is possible for a smaller pulse width to be recognized. t ilih 125 ? ns characteristic (1) 1. v dd = 2.0 vdc 10%, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v ss unless otherwise noted symbol min max unit frequency of operation, (2) crystal option 2. see 20.11 pll2p12m electrical specifications for more information. f osc 32 100 khz internal operating frequency f op ?2.0mhz internal bus cycle time t cyc ? 500 ns reset input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized; it is possible for a smaller pulse width to cause a reset. t irl 125 ? ns irq interrupt pulse width low, (4) edge-triggered 4. minimum pulse width is for guaranteed interrupt; it is possible for a smaller pulse width to be recognized. t ilih 125 ? ns preliminary electrical specifications mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 222 freescale semiconductor 20.9 3.0 volt 10% serial peripheral interface (spi) timing num (1) 1. item numbers refer to dimensions in figure 20-1 and figure 20-2 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted; assumes 100 pf load on all spi pins. symbol min max unit operating frequency master slave f op( m ) f op( s ) f op /128 dc f op /2 f op mhz 1 cycle time master slave t cyc( m ) t cyc( s ) 2 1 128 ? t cyc 2 enable lead time t lead 30 ? ns 3 enable lag time t lag 30 ? ns 4 clock (sck) high time master slave t w ( sckh ) m t w ( sckh ) s 200 100 ? ? ns 5 clock (sck) low time master slave t w ( sckl ) m t w ( sckl ) s 200 100 ? ? ns 6 data setup time, inputs master slave t su ( m ) t su ( s ) 90 10 ? ? ns 7 data hold time, inputs master slave t h ( m ) t h ( s ) 0 30 ? ? ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 80 40 ns 9 slave disable time, hold time to high-impedance state (4) 4. hold time to high-impedance state t dis ?50ns 10 data valid time after enable edge (5) master slave 5. with 100 pf on all spi pins t v ( m ) t v ( s ) ? ? 20 80 ns 11 data hold time, outputs, after enable edge master slave t ho ( m ) t ho ( s ) 0 10 ? ? ns 2.0 volt 10% serial peripheral interface (spi) timing mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 223 20.10 2.0 volt 10% serial peripheral interface (spi) timing num (1) 1. item numbers refer to dimensions in figure 20-1 and figure 20-2 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted; assumes 100 pf load on all spi pins. symbol min max unit operating frequency master slave f op( m ) f op( s ) f op /128 dc f op /2 f op mhz 1 cycle time master slave t cyc( m ) t cyc( s ) 2 1 128 ? t cyc 2 enable lead time t lead 60 ? ns 3 enable lag time t lag 60 ? ns 4 clock (sck) high time master slave t w ( sckh ) m t w ( sckh ) s 400 200 ? ? ns 5 clock (sck) low time master slave t w ( sckl ) m t w ( sckl ) s 400 200 ? ? ns 6 data setup time, inputs master slave t su ( m ) t su ( s ) 180 20 ? ? ns 7 data hold time, inputs master slave t h ( m ) t h ( s ) 0 60 ? ? ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 160 80 ns 9 slave disable time, hold time to high-impedance state (4) 4. hold time to high-impedance state t dis ?100ns 10 data valid time after enable edge (5) master slave 5. with 100 pf on all spi pins t v ( m ) t v ( s ) ? ? 40 160 ns 11 data hold time, outputs, after enable edge master slave t ho ( m ) t ho ( s ) 0 2 ? ? ns preliminary electrical specifications mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 224 freescale semiconductor figure 20-1. spi master timing note note: this first cloc k edge is generated internally, but is not seen at the sck pin. ss pin of master held high. msb in ss input sck (cpol = 0) output sck (cpol = 1) output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 11 7 6 note note: this last clock edge is generated inte rnally, but is not seen at the sck pin. ss pin of master held high. msb in ss input sck (cpol = 0) output sck (cpol = 1) output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 11 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) 2.0 volt 10% serial peripheral interface (spi) timing mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 225 figure 20-2. spi slave timing note: not defined but normally msb of character just received. slave ss input sck (cpol = 0) input sck (cpol = 1) input miso input mosi output 4 5 5 1 4 msb in bits 6?1 8 6 10 11 11 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out note: not defined but normally lsb of character previ ously transmitted. slave ss input sck (cpol = 0) input sck (cpol = 1) input miso output mosi input 4 5 5 1 4 msb in bits 6?1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11 preliminary electrical specifications mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 226 freescale semiconductor 20.11 pll2p12m electrical specifications 20.12 bus clock pll acquisit ion/lock time specifications this section provides specifications for the entry and exit of acquisition and tracking modes, as well as required manual mode delay times. description symbol min typ max notes cgmxclk reference frequency f rclk ? 38.4 khz ? range nominal multiplier (hz) f nom ? 38.4 k ? vco center-of-range frequency (hz) f vrs 38.4 k 38.4 k ? 20.0 m 10.0 m 2.7?3.3 v v dd only 1.8?2.7 v v dd vco range linear range multiplier l 1 e = 0 64 e = 0 255 e = 3 vco power-of-two range multiplier 2 e 11 8 vco multiply factor n 1 64 4095 vco prescale multiplier 2 p 1 p = 0 1 p = 0 8 p = 3 reference divider factor r 1 1 15 vco operating frequency f vclk f vrsmin ? f vrsmax bus operating frequency (hz) f bus ? ? ? ? 4 m 2 m 2.7?3.3 v v dd only 1.8?2.7 v v dd only description symbol min typ max notes filter capacitor multiply factor c fact ? 0.0145 ? f/sv acquisition mode time factor k acq ? 0.117 ? v tracking mode time factor k trk ? 0.021 ? v manual mode time to stable t acq ?10 ms? if c f chosen correctly manual stable to lock time t al ?20 ms? if c f chosen correctly manual acquisition time t lock ? t acq + t al ? tracking mode entry frequency tolerance ? trk 0? 3.6% acquisition mode entry frequency tolerance ? acq 6.3% ? 7.2% lock entry frequency tolerance ? lock 0? 0.9% lock exit frequency tolerance ? unl 0.9% ? 1.8% reference cycles per acquisition mode measurement n acq ?32? reference cycles per tracking mode measurement n trk ?128? automatic mode time to stable t acq n acq /f rdv 10 ms ? if c f chosen correctly automatic stable to lock time t al n trk /f rdv 15 ms ? if c f chosen correctly automatic lock time t lock ? t acq + t al ? pll2p12m component specifications mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 227 20.13 pll2p12m comp onent specifications 20.14 ram characteristics 20.15 flash memory electrical characteristics characteristic symbol min typ max notes crystal load capacitance c l ??? consult crystal manufacturer?s data crystal fixed capacitance c 1 ? 2 x c l ? consult crystal manufacturer?s data crystal tuning capacitance c 2 ? 2 x c l ? consult crystal manufacturer?s data feedback bias resistor r b ? 22 m ? ? series resistor r s 0330 k ? 1 m ? not required filter capacitor c f ? c fact (v dda /f xclk ) ? bypass capacitor c byp ?0.1 f? c byp must provide low ac impedance from f = f xclk /100 to 100 x f vclk , so series resistance must be considered. characteristic symbol min typ max unit ram data retention voltage v rdr 0.7 ? ? v parameter descripti on min typ max units t erase erase time 40 80 110 ms t kill high voltage kill time 200 200 ? s t hvd return to read mode time 50 50 ? s t step program step size 0.8 1.0 1.2 ? pulses number of program pulses/page 1 8 10 pulses t hvtv hven low to verf high time 50 ? ? s t vtp verf high to pgm low time 150 ? ? s endurance erase/program cycles ? ? 100 ????? pump clock frequency charge pump frequency 1.8 ? 2.5 mhz preliminary electrical specifications mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 228 freescale semiconductor mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 229 chapter 21 mechanical data 21.1 introduction the following figures show the latest package drawings at the time of th is publication. to make sure that you have the latest package specifications, contact your local freescale sales office. mechanical data mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 230 freescale semiconductor 21.2 160 input/output, bga, stan dard map, 15 x 15 package (case #1268) x 0.20 laser mark for pin 1 identification in this area e 13x d e m s a1 a2 a 0.15 z 0.30 z z rotated 90 clockwise detail k 5 view m?m e 13x s m x 0.30 y z 0.10 z 3 b 160x metalized mark for pin 1 identification in this area 14 13 12 11 10 9 6 5 4 3 2 1 a b c d e f g h j k l m n p 4 160x notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.32 1.75 a1 0.27 0.47 a2 1.18 ref b 0.35 0.65 d 15.00 bsc e 15.00 bsc e 1.00 bsc s 0.50 bsc y k wire bond information (mcw68hc08lk60) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 231 21.3 wire bond info rmation (mcw68hc08lk60) 21.3.1 die pad coordinates table 21-1. die pad coordinates (sheet 1 of 5) pad number pad function x (microns) x (mils) y (microns) y (mils) 1 ev dd ?2604.3 ?102.53 2519.4 99.19 2 ev ss ?2604.3 ?102.53 2386.8 93.97 3 v dda ?2604.3 ?102.53 2254.2 88.75 4 cgmxfc ?2604.3 ?102.53 2121.6 83.53 5 osc1 ?2604.3 ?102.53 1989 78.31 6 osc2 ?2604.3 ?102.53 1856.4 73.09 7 v ssa ?2604.3 ?102.53 1723.8 67.87 8 v dd ?2604.3 ?102.53 1591.2 62.65 9 v ss ?2604.3 ?102.53 1458.6 57.43 10 lcdbp0 ?2604.3 ?102.53 1326 52.20 11 lcdbp1 ?2604.3 ?102.53 1193.4 46.98 12 lcdbp2 ?2604.3 ?102.53 1060.8 41.76 13 lcdbp3 ?2604.3 ?102.53 928.2 36.54 14 lcdfp1 ?2604.3 ?102.53 795.6 31.32 15 lcdfp2 ?2604.3 ?102.53 663 26.10 16 lcdfp3 ?2604.3 ?102.53 530.4 20.88 17 lcdfp4 ?2604.3 ?102.53 397.8 15.66 18 lcdfp5 ?2604.3 ?102.53 265.2 10.44 19 lcdfp6 ?2604.3 ?102.53 132.6 5.22 20 lcdfp7 ?2604.3 ?102.53 0 0.00 21 lcdfp8 ?2604.3 ?102.53 ?132.6 ?5.22 22 lcdfp9 ?2604.3 ?102.53 ?265.2 ?10.44 23 lcdfp10 ?2604.3 ?102.53 ?397.8 ?15.66 24 lcdfp11 ?2604.3 ?102.53 ?530.4 ?20.88 25 lcdfp12 ?2604.3 ?102.53 ?663 ?26.10 26 lcdfp13 ?2604.3 ?102.53 ?795.6 ?31.32 27 lcdfp14 ?2604.3 ?102.53 ?928.2 ?36.54 28 lcdfp15 ?2604.3 ?102.53 ?1060.8 ?41.76 29 lcdfp16 ?2604.3 ?102.53 ?1193.4 ?46.98 30 lcdfp17 ?2604.3 ?102.53 ?1326 ?52.20 mechanical data mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 232 freescale semiconductor 31 lcdfp18 ?2604.3 ?102.53 ?1458.6 ?57.43 32 lcdfp19 ?2604.3 ?102.53 ?1591.2 ?62.65 33 lcdfp20 ?2604.3 ?102.53 ?1723.8 ?67.87 34 lcdfp21 ?2604.3 ?102.53 ?1856.4 ?73.09 35 lcdfp22 ?2604.3 ?102.53 ?1989 ?78.31 36 lcdfp23 ?2604.3 ?102.53 ?2121.6 ?83.53 37 lcdfp24 ?2604.3 ?102.53 ?2254.2 ?88.75 38 lcdfp25 ?2604.3 ?102.53 ?2386.8 ?93.97 39 lcdfp26 ?2604.3 ?102.53 ?2519.4 ?99.19 40 lcdfp27 ?2320.5 ?91.36 ?2803.2 ?110.36 41 lcdfp28 ?2187.9 ?86.14 ?2803.2 ?110.36 42 lcdfp29 ?2055.3 ?80.92 ?2803.2 ?110.36 43 lcdfp30 ?1922.7 ?75.70 ?2803.2 ?110.36 44 lcdfp31 ?1790.1 ?70.48 ?2803.2 ?110.36 45 lcdfp32 ?1657.5 ?65.26 ?2803.2 ?110.36 46 lcdfp33 ?1524.9 ?60.04 ?2803.2 ?110.36 47 lcdfp34 ?1392.3 ?54.81 ?2803.2 ?110.36 48 lcdfp35 ?1259.7 ?49.59 ?2803.2 ?110.36 49 lcdfp36 ?1127.1 ?44.37 ?2803.2 ?110.36 50 lcdfp37 ?994.5 ?39.15 ?2803.2 ?110.36 51 lcdfp38 ?861.9 ?33.93 ?2803.2 ?110.36 52 lcdfp39 ?729.3 ?28.71 ?2803.2 ?110.36 53 lcdfp40 ?596.7 ?23.49 ?2803.2 ?110.36 54 lcdfp41 ?464.1 ?18.27 ?2803.2 ?110.36 55 lcdfp42 ?331.5 ?13.05 ?2803.2 ?110.36 56 lcdfp43 ?198.9 ?7.83 ?2803.2 ?110.36 57 v ll ?66.3 ?2.61 ?2803.2 ?110.36 58 vcp1 66.3 2.61 ?2803.2 ?110.36 59 vcp2 198.9 7.83 ?2803.2 ?110.36 60 vcp3 331.5 13.05 ?2803.2 ?110.36 61 vcp4 464.1 18.27 ?2803.2 ?110.36 62 v ll12 596.7 23.49 ?2803.2 ?110.36 63 v ll32 729.3 28.71 ?2803.2 ?110.36 64 lcdfp44 861.9 33. 93 ?2803.2 ?110.36 table 21-1. die pad coordinates (sheet 2 of 5) pad number pad function x (microns) x (mils) y (microns) y (mils) wire bond information (mcw68hc08lk60) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 233 65 lcdfp45 994.5 39. 15 ?2803.2 ?110.36 66 lcdfp46 1127.1 44.37 ?2803.2 ?110.36 67 lcdfp47 1259.7 49.59 ?2803.2 ?110.36 68 lcdfp48 1392.3 54.81 ?2803.2 ?110.36 69 lcdfp49 1524.9 60.04 ?2803.2 ?110.36 70 lcdfp50 1657.5 65.26 ?2803.2 ?110.36 71 lcdfp51 1790.1 70.48 ?2803.2 ?110.36 72 lcdfp52 1922.7 75.70 ?2803.2 ?110.36 73 lcdfp53 2055.3 80.92 ?2803.2 ?110.36 74 lcdfp54 2187.9 86.14 ?2803.2 ?110.36 75 lcdfp55 2320.5 91.36 ?2803.2 ?110.36 76 lcdfp56 2604.3 102.53 ?2519.4 ?99.19 77 lcdfp57 2604.3 102.53 ?2386.8 ?93.97 78 lcdfp58 2604.3 102.53 ?2254.2 ?88.75 79 lcdfp59 2604.3 102.53 ?2121.6 ?83.53 80 lcdfp60 2604.3 102.53 ?1989 ?78.31 81 lcdfp61 2604.3 102.53 ?1856.4 ?73.09 82 lcdfp62 2604.3 102.53 ?1723.8 ?67.87 83 lcdfp63 2604.3 102.53 ?1591.2 ?62.65 84 lcdfp64 2604.3 102.53 ?1458.6 ?57.43 85 lcdfp65 2604.3 102.53 ?1326 ?52.20 86 lcdfp66 2604.3 102.53 ?1193.4 ?46.98 87 lcdfp67 2604.3 102.53 ?1060.8 ?41.76 88 lcdfp68 2604.3 102.53 ?928.2 ?36.54 89 lcdfp69 2604.3 102.53 ?795.6 ?31.32 90 lcdfp70 2604.3 102.53 ?663 ?26.10 91 lcdfp71 2604.3 102.53 ?530.4 ?20.88 92 lcdfp72 2604.3 102.53 ?397.8 ?15.66 93 lcdfp73 2604.3 102.53 ?265.2 ?10.44 94 lcdfp74 2604.3 102.53 ?132.6 ?5.22 95 lcdfp75 2604.3 102.53 0 0.00 96 lcdfp76 2604.3 102.53 132.6 5.22 97 lcdfp77 2604.3 102.53 265.2 10.44 98 lcdfp78 2604.3 102.53 397.8 15.66 table 21-1. die pad coordinates (sheet 3 of 5) pad number pad function x (microns) x (mils) y (microns) y (mils) mechanical data mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 234 freescale semiconductor 99 lcdfp79 2604.3 102.53 530.4 20.88 100 lcdfp80 2604.3 102.53 663 26.10 101 lcdfp81 2604.3 102.53 795.6 31.32 102 lcdfp82 2604.3 102.53 928.2 36.54 103 lcdfp83 2604.3 102.53 1060.8 41.76 104 lcdfp84 2604.3 102.53 1193.4 46.98 105 lcdfp85 2604.3 102.53 1326 52.20 106 lcdbp4 2604.3 102.53 1458.6 57.43 107 lcdbp5 2604.3 102.53 1591.2 62.65 108 lcdbp6 2604.3 102.53 1723.8 67.87 109 lcdbp7 2604.3 102.53 1856.4 73.09 110 v ss 2604.3 102.53 1989 78.31 111 v dd 2604.3 102.53 2121.6 83.53 112 alert 2604.3 102.53 2254.2 88.75 113 ekbib 2604.3 102.53 2386.8 93.97 114 ev ss 2604.3 102.53 2519.4 99.19 115 ev dd 2320.5 91.36 2803.2 110.36 116 ptc0 2187.9 86.14 2803.2 110.36 117 ptc1 2055.3 80.92 2803.2 110.36 118 ptc2 1922.7 75.70 2803.2 110.36 119 ptc3 1790.1 70.48 2803.2 110.36 120 ptc4 1657.5 65.26 2803.2 110.36 121 ptc5 1524.9 60.04 2803.2 110.36 122 ptc6 1392.3 54.81 2803.2 110.36 123 ptc7 1259.7 49.59 2803.2 110.36 124 ev ss 1127.1 44.37 2803.2 110.36 125 ptb0 994.5 39.15 2803.2 110.36 126 ptb1 861.9 33.93 2803.2 110.36 127 ptb2 729.3 28.71 2803.2 110.36 128 ptb3 596.7 23.49 2803.2 110.36 129 ptb4 464.1 18.27 2803.2 110.36 130 ptb5 331.5 13.05 2803.2 110.36 131 ptb6 198.9 7.83 2803.2 110.36 132 ptb7 66.3 2.61 2803.2 110.36 table 21-1. die pad coordinates (sheet 4 of 5) pad number pad function x (microns) x (mils) y (microns) y (mils) wire bond information (mcw68hc08lk60) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 235 133 pta0 ?66.3 ?2.61 2803.2 110.36 134 pta1 ?198.9 ?7.83 2803.2 110.36 135 pta2 ?331.5 ?13.05 2803.2 110.36 136 pta3 ?464.1 ?18.27 2803.2 110.36 137 pta4 ?596.7 ?23.49 2803.2 110.36 138 pta5 ?729.3 ?28.71 2803.2 110.36 139 pta6 ?861.9 ?33.93 2803.2 110.36 140 pta7 ?994.5 ?39.15 2803.2 110.36 141 irq2b ?1127.1 ?44.37 2803.2 110.36 142 irq1b ?1259.7 ?49.59 2803.2 110.36 143 ev ss ?1392.3 ?54.81 2803.2 110.36 144 sck ?1524.9 ?60.04 2803.2 110.36 145 mosi ?1657.5 ?65.26 2803.2 110.36 146 miso ?1790.1 ?70.48 2803.2 110.36 147 ssb ?1922.7 ?75.70 2803.2 110.36 148 tdo ?2055.3 ?80.92 2803.2 110.36 149 rdi ?2187.9 ?86.14 2803.2 110.36 150 rstb ?2320.5 ?91.36 2803.2 110.36 table 21-1. die pad coordinates (sheet 5 of 5) pad number pad function x (microns) x (mils) y (microns) y (mils) mechanical data mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 236 freescale semiconductor 21.3.2 die layout figure 21-1. 68hc08lk60 die layout bump wafer information (mccf68hc08lk60) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 237 21.4 bump wafer info rmation (mccf68hc08lk60) 21.4.1 bump specification figure 21-2. bump specification smd electroplated bump : dimensions before probe tiwn x /tiw/cu die passivation lk60 bump sputtered layers cu stud reflowed solder 63%sn 5% 45 5m 118 +10/-5 m al pad 160 5 m ref. 4.9-6.7 mils c l mechanical data mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 238 freescale semiconductor 21.4.2 bumped wafer pad coordinates table 21-2. bump coordinates (sheet 1 of 5) bump pad number bump pad name x (microns) x (mils) y (microns) y (mils) 1 ev dd ?2006.6 ?79.00 1728 68.03 2 ev ss ?1066.8 ?42.00 812 31.97 3 v dda ?2413 ?95.00 2336 91.97 4 cgmxfc ?2413 ?95.00 2082 81.97 5 osc1 ?2006.6 ?79.00 1474 58.03 6 osc2 ?1066.8 ?42.00 50 1.97 7 v ssa ?1066.8 ?42.00 558 21.97 8 v dd ?2413 ?95.00 1474 58.03 9 v ss ?1066.8 ?42.00 304 11.97 10 lcdbp0 ?2413 ?95.00 1728 68.03 11 lcdbp1 ?2413 ?95.00 1220 48.03 12 lcdbp2 ?2006.6 ?79.00 1220 48.03 13 lcdbp3 ?2413 ?95.00 966 38.03 14 lcdfp1 ?2413 ?95.00 712 28.03 15 lcdfp2 ?2006.6 ?79.00 966 38.03 16 lcdfp3 ?2413 ?95.00 458 18.03 17 lcdfp4 ?2006.6 ?79.00 712 28.03 18 lcdfp5 ?2413 ?95.00 204 8.03 19 lcdfp6 ?2006.6 ?79.00 458 18.03 20 lcdfp7 ?2413 ?95.00 ?50 ?1.97 21 lcdfp8 ?2006.6 ?79.00 204 8.03 22 lcdfp9 ?2413 ?95.00 ?304 ?11.97 23 lcdfp10 ?2006.6 ?79.00 ?50 ?1.97 24 lcdfp11 ?2413 ?95.00 ?558 ?21.97 25 lcdfp12 ?2006.6 ?79.00 ?304 ?11.97 26 lcdfp13 ?2413 ?95.00 ?812 ?31.97 27 lcdfp14 ?2006.6 ?79.00 ?558 ?21.97 28 lcdfp15 ?2413 ?95.00 ?1066 ?41.97 29 lcdfp16 ?2006.6 ?79.00 ?812 ?31.97 30 lcdfp17 ?2413 ?95.00 ?1320 ?51.97 31 lcdfp18 ?2006.6 ?79.00 ?1066 ?41.97 32 lcdfp19 ?2413 ?95.00 ?1574 ?61.97 bump wafer information (mccf68hc08lk60) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 239 33 lcdfp20 ?2006.6 ?79.00 ?1320 ?51.97 34 lcdfp21 ?2413 ?95.00 ?1828 ?71.97 35 lcdfp22 ?2006.6 ?79.00 ?1574 ?61.97 36 lcdfp23 ?2413 ?95.00 ?2082 ?81.97 37 lcdfp24 ?1066.8 ?42.00 ?204 ?8.03 38 lcdfp25 ?2413 ?95.00 ?2336 ?91.97 39 lcdfp26 ?2006.6 ?79.00 ?1828 ?71.97 40 lcdfp27 ?1651 ?65.00 ?2183.6 ?85.97 41 lcdfp28 ?2159 ?85.00 ?2590 ?101.97 42 lcdfp29 ?1066.8 ?42.00 ?458 ?18.03 43 lcdfp30 ?1905 ?75.00 ?2590 ?101.97 44 lcdfp31 ?1397 ?55.00 ?2183.6 ?85.97 45 lcdfp32 ?1651 ?65.00 ?2590 ?101.97 46 lcdfp33 ?1066.8 ?42.00 ?712 ?28.03 47 lcdfp34 ?1397 ?55.00 ?2590 ?101.97 48 lcdfp35 ?1143 ?45.00 ?2183.6 ?85.97 49 lcdfp36 ?1143 ?45.00 ?2590 ?101.97 50 lcdfp37 ?889 ?35.00 ?2183.6 ?85.97 51 lcdfp38 ?889 ?35.00 ?2590 ?101.97 52 lcdfp39 ?635 ?25.00 ?2183.6 ?85.97 53 lcdfp40 ?635 ?25.00 ?2590 ?101.97 54 lcdfp41 ?381 ?15.00 ?2183.6 ?85.97 55 lcdfp42 ?381 ?15.00 ?2590 ?101.97 56 lcdfp43 ?127 ?5.00 ?2183.6 ?85.97 57 v ll ?127 ?5.00 ?2590 ?101.97 58 vcp1 127 5.00 ?2590 ?101.97 59 vcp2 127 5.00 ?2183.6 ?85.97 60 vcp3 381 15.00 ?2590 ?101.97 61 vcp4 381 15.00 ?2183.6 ?85.97 62 v ll12 635 25.00 ?2590 ?101.97 63 v ll32 635 25.00 ?2183.6 ?85.97 64 lcdfp44 889 35.00 ?2590 ?101.97 65 lcdfp45 889 35.00 ?2183.6 ?85.97 66 lcdfp46 1066.8 42.00 304 11.97 table 21-2. bump coordinates (sheet 2 of 5) bump pad number bump pad name x (microns) x (mils) y (microns) y (mils) mechanical data mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 240 freescale semiconductor 67 lcdfp47 1143 45.00 ?2590 ?101.97 68 lcdfp48 1143 45.00 ?2183.6 ?85.97 69 lcdfp49 1397 55.00 ?2590 ?101.97 70 lcdfp50 1066.8 42.00 50 1.97 71 lcdfp51 1651 65.00 ?2590 ?101.97 72 lcdfp52 1905 75.00 ?2590 ?101.97 73 lcdfp53 1397 55.00 ?2183.6 ?85.97 74 lcdfp54 2159 85.00 ?2590 ?101.97 75 lcdfp55 1651 65.00 ?2183.6 ?85.97 76 lcdfp56 1066.8 42.00 558 21.97 77 lcdfp57 1066.8 42.00 812 31.97 78 lcdfp58 2413 95.00 ?2236 ?88.03 79 lcdfp59 2006.6 79.00 ?1728 ?68.03 80 lcdfp60 2413 95.00 ?1982 ?78.03 81 lcdfp61 2006.6 79.00 ?1474 ?58.03 82 lcdfp62 2413 95.00 ?1728 ?68.03 83 lcdfp63 2006.6 79.00 ?1220 ?48.03 84 lcdfp64 2413 95.00 ?1474 ?58.03 85 lcdfp65 2006.6 79.00 ?966 ?38.03 86 lcdfp66 2413 95.00 ?1220 ?48.03 87 lcdfp67 2006.6 79.00 ?712 ?28.03 88 lcdfp68 2413 95.00 ?966 ?38.03 89 lcdfp69 2006.6 79.00 ?458 ?18.03 90 lcdfp70 2413 95.00 ?712 ?28.03 91 lcdfp71 2006.6 79.00 ?204 ?8.03 92 lcdfp72 2413 95.00 ?458 ?18.03 93 lcdfp73 2413 95.00 ?204 ?8.03 94 lcdfp74 2006.6 79.00 50 1.97 95 lcdfp75 2413 95.00 50 1.97 96 lcdfp76 2006.6 79.00 304 11.97 97 lcdfp77 2413 95.00 304 11.97 98 lcdfp78 2006.6 79.00 558 21.97 99 lcdfp79 2413 95.00 558 21.97 100 lcdfp80 2006.6 79.00 812 31.97 table 21-2. bump coordinates (sheet 3 of 5) bump pad number bump pad name x (microns) x (mils) y (microns) y (mils) bump wafer information (mccf68hc08lk60) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 241 101 lcdfp81 2413 95.00 812 31.97 102 lcdfp82 2006.6 79.00 1066 41.97 103 lcdfp83 2413 95.00 1066 41.97 104 lcdfp84 635 25.00 1243.8 48.97 105 lcdfp85 2413 95.00 1320 51.97 106 lcdbp4 2006.6 79.00 1320 51.97 107 lcdbp5 2413 95.00 1574 61.97 108 lcdbp6 381 15.00 1243.8 48.97 109 lcdbp7 2413 95.00 1828 71.97 110 v ss 2006.6 79.00 1574 61.97 111 v dd 2413 95.00 2082 81.97 112 alert 127 5.00 1243.8 48.97 113 ekbib 2413 95.00 2336 91.97 114 ev ss 2006.6 79.00 1828 71.97 115 ev dd 2159 85.00 2590 101.97 116 ptc0 ?127 ?5.00 1243.8 48.97 117 ptc1 ?381 ?15.00 1243.8 48.97 118 ptc2 1905 75.00 2590 101.97 119 ptc3 1651 65.00 2183.6 85.97 120 ptc4 1651 65.00 2590 101.97 121 ptc5 1397 55.00 2183.6 85.97 122 ptc6 1397 55.00 2590 101.97 123 ptc7 1143 45.00 2590 101.97 124 ev ss 1143 45.00 2183.6 85.97 125 ptb0 889 35.00 2183.6 85.97 126 ptb1 889 35.00 2590 101.97 127 ptb2 635 25.00 2183.6 85.97 128 ptb3 635 25.00 2590 101.97 129 ptb4 381 15.00 2183.6 85.97 130 ptb5 381 15.00 2590 101.97 131 ptb6 127 5.00 2590 101.97 132 ptb7 127 5.00 2183.6 85.97 133 pta0 ?127 ?5.00 2590 101.97 134 pta1 ?127 ?5.00 2183.6 85.97 table 21-2. bump coordinates (sheet 4 of 5) bump pad number bump pad name x (microns) x (mils) y (microns) y (mils) mechanical data mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 242 freescale semiconductor 135 pta2 ?381 ?15.00 2590 101.97 136 pta3 ?381 ?15.00 2183.6 85.97 137 pta4 ?635 ?25.00 2590 101.97 138 pta5 ?635 ?25.00 2183.6 85.97 139 pta6 ?889 ?35.00 2590 101.97 140 pta7 ?635 ?25.00 1243.8 48.97 141 irq2b ?1143 ?45.00 2590 101.97 142 irq1b ?889 ?35.00 2183.6 85.97 143 ev ss ?889 ?35.00 1243.8 48.97 144 sck ?1397 ?55.00 2590 101.97 145 mosi ?1651 ?65.00 2590 101.97 146 miso ?1143 ?45.00 2183.6 85.97 147 ssb ?1905 ?75.00 2590 101.97 148 tdo ?1397 ?55.00 2183.6 85.97 149 rdi ?1651 ?65.00 2183.6 85.97 150 rstb ?2159 ?85.00 2590 101.97 table 21-2. bump coordinates (sheet 5 of 5) bump pad number bump pad name x (microns) x (mils) y (microns) y (mils) bump wafer information (mccf68hc08lk60) mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 243 21.4.3 die feature figure 21-3. bump die layout mechanical data mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 244 freescale semiconductor 21.4.4 tape and reel die orientation figure 21-4. tape and reel die orientation note: active side down (b umps side), x-ray top view mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 freescale semiconductor 245 chapter 22 ordering information 22.1 introduction this section contains instructions for ordering the mc68hc(9)08lk60. 22.2 mc order numbers table 22-1. mc order numbers mc order number operating temperature range description MC68HC08LK60VF ?20 to +65 c bga package mcw68hc08lk60 ?20 to +65 c wafer sales mccf68hc08lk60 ?20 to +65 c bump wafer sales note: tested and guaranteed at room temperature only. ordering information mc68hc08lk60 mc68hc908lk60 advance information data sheet, rev. 1.1 246 freescale semiconductor how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data shee ts and/or specificati ons can and do vary in different applications and actual perfo rmance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2005. all rights reserved. mc68hc08lk60 rev. 1.1, 09/2005 |
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